Issued Patents All Time
Showing 226–250 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11688626 | Nanosheet transistor with self-aligned dielectric pillar | Kangguo Cheng, Julien Frougier | 2023-06-27 |
| 11683998 | Vertical phase change bridge memory cell | Juntao Li, Kangguo Cheng, Carl Radens | 2023-06-20 |
| 11665877 | Stacked FET SRAM design | Chen Zhang, Junli Wang, Dechao Guo | 2023-05-30 |
| 11664455 | Wrap-around bottom contact for bottom source/drain | Junli Wang, Alexander Reznicek, Bruce B. Doris | 2023-05-30 |
| 11652156 | Nanosheet transistor with asymmetric gate stack | Carl Radens, Kangguo Cheng, Juntao Li, Dechao Guo, Tao Li +1 more | 2023-05-16 |
| 11646373 | Vertical field effect transistor with bottom spacer | Christopher J. Waskiewicz, Jay William Strane, Hemanth Jagannathan | 2023-05-09 |
| 11646362 | Vertical transport field-effect transistor structure having increased effective width and self-aligned anchor for source/drain region formation | Alexander Reznicek, Takashi Ando, Pouya Hashemi | 2023-05-09 |
| 11646306 | Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate | Julien Frougier, Veeraraghavan S. Basker, Andrew Gaul | 2023-05-09 |
| 11637238 | Resistive random-access memory cell and manufacturing method thereof | Kangguo Cheng, Chanro Park, Juntao Li | 2023-04-25 |
| 11637179 | Airgap vertical transistor without structural collapse | Kangguo Cheng, Chanro Park, Juntao Li | 2023-04-25 |
| 11631617 | Scalable device for FINFET technology | Kangguo Cheng, Juntao Li, Chanro Park | 2023-04-18 |
| 11626287 | Semiconductor device with improved contact resistance and via connectivity | Chanro Park, Kangguo Cheng, Juntao Li | 2023-04-11 |
| 11621333 | Gate contact structure for a transistor device | Hao Tang, Cheng Chi, Daniel Chanemougame, Lars Liebmann, Mark V. Raymond | 2023-04-04 |
| 11621332 | Wraparound contact to a buried power rail | Veeraraghavan S. Basker, Alexander Reznicek, Junli Wang | 2023-04-04 |
| 11621326 | Vertical field effect transistor with crosslink fin arrangement | Indira Seshadri, Chen Zhang, Ekmini Anuja De Silva | 2023-04-04 |
| 11621269 | Multi-level ferroelectric memory cell | Julien Frougier | 2023-04-04 |
| 11621199 | Silicide formation for source/drain contact in a vertical transport field-effect transistor | Heng Wu, Su Chen Fan, Huai Huang | 2023-04-04 |
| 11616140 | Vertical transport field effect transistor with bottom source/drain | Heng Wu, Gen Tsutsui, Lan Yu | 2023-03-28 |
| 11615990 | CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor | Heng Wu, Su Chen Fan, Jay William Strane, Hemanth Jagannathan | 2023-03-28 |
| 11605717 | Wrapped-around contact for vertical field effect transistor top source-drain | Eric R. Miller, Jeffrey C. Shearer, Su Chen Fan, Heng Wu | 2023-03-14 |
| 11605672 | Steep-switch field effect transistor with integrated bi-stable resistive system | Julien Frougier, Nicolas Loubet, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng | 2023-03-14 |
| 11605409 | MTJ-based analog memory device | Dimitri Houssameddine, Julien Frougier, Kangguo Cheng | 2023-03-14 |
| 11588104 | Resistive memory with vertical transport transistor | Kangguo Cheng, Carl Radens, Juntao Li | 2023-02-21 |
| 11575025 | Vertical field effect transistor with self-aligned source and drain top junction | Chun-Chen Yeh, Alexander Reznicek, Chen Zhang | 2023-02-07 |
| 11575023 | Secure chip identification using random threshold voltage variation in a field effect transistor structure as a physically unclonable function | Clint Jason Oteri, Alexander Reznicek, Bahman Hekmatshoartabari, Jingyun Zhang | 2023-02-07 |