Issued Patents All Time
Showing 201–225 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11769796 | Hybrid complementary metal-oxide semiconductor field effect transistor nanosheet device | Chen Zhang, Tenko Yamashita | 2023-09-26 |
| 11764298 | VTFET with buried power rails | Chen Zhang, Heng Wu, Junli Wang, Brent A. Anderson | 2023-09-19 |
| 11764265 | Nanosheet transistor with inner spacers | Kangguo Cheng, Julien Frougier, Juntao Li | 2023-09-19 |
| 11757036 | Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices | Chen Zhang, Julien Frougier, Alexander Reznicek, Shogo Mochizuki | 2023-09-12 |
| 11749744 | Fin structure for vertical transport field effect transistor | Heng Wu, Lan Yu, Dechao Guo, Junli Wang, Ruqiang Bao | 2023-09-05 |
| 11742426 | Forming crossbar and non-crossbar transistors on the same substrate | Indira Seshadri, Ardasheir Rahman, Hemanth Jagannathan | 2023-08-29 |
| 11742425 | FinFET device with partial interface dipole formation for reduction of gate induced drain leakage | Takashi Ando, Alexander Reznicek, Pouya Hashemi | 2023-08-29 |
| 11742354 | Top epitaxial layer and contact for VTFET | Christopher J. Waskiewicz, Alexander Reznicek, Su Chen Fan, Heng Wu | 2023-08-29 |
| 11742350 | Metal gate N/P boundary control by active gate cut and recess | Andrew Gaul, Chanro Park, Julien Frougier, Andrew M. Greene, Christopher J. Waskiewicz | 2023-08-29 |
| 11742246 | Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors | Hemanth Jagannathan, Christopher J. Waskiewicz, Alexander Reznicek | 2023-08-29 |
| 11737289 | High density ReRAM integration with interconnect | Takashi Ando, Alexander Reznicek, Pouya Hashemi | 2023-08-22 |
| 11735628 | Nanosheet metal-oxide semiconductor field effect transistor with asymmetric threshold voltage | Takashi Ando, Alexander Reznicek, Jingyun Zhang | 2023-08-22 |
| 11735590 | Fin stack including tensile-strained and compressively strained fin portions | Kangguo Cheng, Julien Frougier, Chanro Park | 2023-08-22 |
| 11735480 | Transistor having source or drain formation assistance regions with improved bottom isolation | Alexander Reznicek, Effendi Leobandung, Jingyun Zhang | 2023-08-22 |
| 11729996 | High retention eMRAM using VCMA-assisted writing | Heng Wu, Julien Frougier, Bruce B. Doris | 2023-08-15 |
| 11728433 | Vertical transistor with self-aligned gate | Juntao Li, Kangguo Cheng, Chanro Park | 2023-08-15 |
| 11715794 | VTFET with cell height constraints | Heng Wu, Lan Yu, Alexander Reznicek, Junli Wang | 2023-08-01 |
| 11710699 | Complementary FET (CFET) buried sidewall contact with spacer foot | Jingyun Zhang, Reinaldo Vega, Kangguo Cheng | 2023-07-25 |
| 11696518 | Hybrid non-volatile memory cell | Kangguo Cheng, Carl Radens, Juntao Li | 2023-07-04 |
| 11695057 | Protective bilayer inner spacer for nanosheet devices | Yao Yao, Andrew M. Greene, Veeraraghavan S. Basker | 2023-07-04 |
| 11695038 | Forming single and double diffusion breaks for fin field-effect transistor structures | Juntao Li, Kangguo Cheng, Junli Wang | 2023-07-04 |
| 11695004 | Vertical bipolar junction transistor and vertical field effect transistor with shared floating region | Alexander Reznicek, Jeng-Bang Yau, Bahman Hekmatshoartabari | 2023-07-04 |
| 11690305 | Phase change memory cell with an airgap to allow for the expansion and restriction of the PCM material | Kangguo Cheng, Carl Radens, Juntao Li | 2023-06-27 |
| 11688741 | Gate-all-around devices with isolated and non-isolated epitaxy regions for strain engineering | Andrew M. Greene, Julien Frougier, Jingyun Zhang, Sung-Dae Suk, Veeraraghavan S. Basker | 2023-06-27 |
| 11688646 | Reduced source/drain coupling for CFET | Alexander Reznicek, Chanro Park, Chun-Chen Yeh | 2023-06-27 |