Issued Patents All Time
Showing 151–175 of 635 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10957583 | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs | Sean D. Burns, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot, Christopher J. Penny +2 more | 2021-03-23 |
| 10957582 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Michael Rizzolo, Terry A. Spooner, Theodorus E. Standaert | 2021-03-23 |
| 10957581 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Michael Rizzolo, Terry A. Spooner, Theodorus E. Standaert | 2021-03-23 |
| 10950787 | Method having resistive memory crossbar array employing selective barrier layer growth | Takashi Ando, Chih-Chao Yang | 2021-03-16 |
| 10950722 | Vertical gate all-around transistor | John H. Zhang, Carl Radens, Yiheng Xu | 2021-03-16 |
| 10950662 | Resistive memory device with meshed electrodes | Takashi Ando, Chih-Chao Yang, Michael Rizzolo | 2021-03-16 |
| 10943972 | Precision BEOL resistors | Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang | 2021-03-09 |
| 10943866 | Method and structure to construct cylindrical interconnects to reduce resistance | Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Hosadurga Shobha | 2021-03-09 |
| 10937653 | Multiple patterning scheme integration with planarized cut patterning | Hsueh-Chung Chen, Yongan Xu, Yann Mignot, Cornelius Brown Peethala | 2021-03-02 |
| 10936782 | Semiconductor process modeling to enable skip via in place and route flow | Dongbing Shao, Zheng Xu | 2021-03-02 |
| 10930553 | Forming self-aligned vias and air-gaps in semiconductor fabrication | Carl Radens, John H. Zhang | 2021-02-23 |
| 10923575 | Low resistance contact for transistors | Junli Wang, Kirk D. Peterson, Baozhen Li, Terry A. Spooner, John E. Sheets, II | 2021-02-16 |
| 10916699 | Resistive memory crossbar array employing selective barrier layer growth | Takashi Ando, Chih-Chao Yang | 2021-02-09 |
| 10916501 | Back end of line electrical fuse structure and method of fabrication | Benjamin D. Briggs, Michael Rizzolo, Chih-Chao Yang | 2021-02-09 |
| 10916154 | Language learning and speech enhancement through natural language processing | Mahmoud Amin, Zhenxing Bi, Leigh Anne H. Clevenger, Christopher J. Penny, Krishna R. Tunga +1 more | 2021-02-09 |
| 10915620 | Paint on micro chip touch screens | Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Leigh Anne H. Clevenger, Michael Rizzolo +1 more | 2021-02-09 |
| 10912986 | Dynamic rigidity mechanism | Benjamin D. Briggs, Bartlet H. DeProspo, Michael Rizzolo | 2021-02-09 |
| 10901317 | Extreme ultraviolet (EUV) lithography patterning methods utilizing EUV resist hardening | Benjamin D. Briggs, Michael Rizzolo, Ekmini Anuja De Silva, Chih-Chao Yang | 2021-01-26 |
| 10830841 | Magnetic tunnel junction performance monitoring based on magnetic field coupling | Nicholas Anthony Lanzillo, Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis | 2020-11-10 |
| 10832945 | Techniques to improve critical dimension width and depth uniformity between features with different layout densities | Nicole Saulnier, Indira Seshadri, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie +3 more | 2020-11-10 |
| 10833204 | Multiple width nanosheet devices | Kangguo Cheng, Carl Radens, Junli Wang, John H. Zhang | 2020-11-10 |
| 10831973 | Semiconductor process modeling to enable skip via in place and route flow | Dongbing Shao, Zheng Xu | 2020-11-10 |
| 10833010 | Integration of artificial intelligence devices | Hsueh-Chung Chen, Fee Li Lie, Effendi Leobandung | 2020-11-10 |
| 10833266 | Resistive memory crossbar array with ruthenium protection layer | Takashi Ando, Michael Rizzolo, Chih-Chao Yang | 2020-11-10 |
| 10833127 | Three-dimensional and planar memory device co-integration | Takashi Ando, Michael Rizzolo, Chih-Chao Yang | 2020-11-10 |