Issued Patents All Time
Showing 351–375 of 584 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7884475 | Conductor structure including manganese oxide capping layer | Stephen E. Luce | 2011-02-08 |
| 7871919 | Structures and methods for improving solder bump connections in semiconductor devices | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan | 2011-01-18 |
| 7871920 | Semiconductor chips with reduced stress from underfill at edge of chip | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2011-01-18 |
| 7867897 | Low leakage metal-containing cap process using oxidation | Jason P. Gill, Sean Smith, Jean Wynne | 2011-01-11 |
| 7862987 | Method for forming an electrical structure comprising multiple photosensitive materials | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2011-01-04 |
| 7863734 | Dual-sided chip attached modules | Kerry Bernstein, Timothy J. Dalton, Timothy H. Daubenspeck, Mark D. Jaffe, Christopher D. Muzzy +3 more | 2011-01-04 |
| 7859122 | Final via structures for bond pad-solder ball interconnections | Timothy H. Daubenspeck, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter | 2010-12-28 |
| 7847409 | Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner | Anthony K. Stamper | 2010-12-07 |
| 7843069 | Wire bond pads | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2010-11-30 |
| 7829945 | Lateral diffusion field effect transistor with asymmetric gate dielectric profile | James W. Adkisson, Natalie B. Feilchenfeld, Benjamin T. Voegeli, Michael J. Zierak | 2010-11-09 |
| 7824961 | Stacked imager package | James W. Adkisson, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce, Richard J. Rassel +1 more | 2010-11-02 |
| 7825416 | Image sensor including spatially different active and dark pixel interconnect patterns | Mark D. Jaffe, Robert K. Leidy, Richard J. Rassel | 2010-11-02 |
| 7825511 | Undercut-free BLM process for Pb-free and Pb-reduced C4 | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2010-11-02 |
| 7816738 | Low-cost FEOL for ultra-low power, near sub-vth device structures | Brent A. Anderson, Andres Bryant, William F. Clark, Jr., Shih-Fen Huang, Edward J. Nowak +1 more | 2010-10-19 |
| 7790559 | Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes | James W. Adkisson, Michael P. Chudzik, Hongwen Yan | 2010-09-07 |
| 7781321 | Electroless metal deposition for dual work function | Michael P. Chudzik, Renee T. Mo | 2010-08-24 |
| 7781267 | Enclosed nanotube structure and method for forming | Son V. Nguyen | 2010-08-24 |
| 7781292 | High power device isolation and integration | Steven H. Voldman, Michael J. Zierak | 2010-08-24 |
| 7781781 | CMOS imager array with recessed dielectric | James W. Adkisson, Zhong-Xiang He, Mark D. Jaffe, Robert K. Leidy, Stephen E. Luce +2 more | 2010-08-24 |
| 7777339 | Semiconductor chips with reduced stress from underfill at edge of chip | Timothy H. Daubenspeck, Christopher D. Muzzy, Wolfgang Sauter | 2010-08-17 |
| 7772028 | CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom | James W. Adkisson, Mark D. Jaffe, Robert K. Leidy, Richard J. Rassel, Anthony K. Stamper | 2010-08-10 |
| 7763954 | Post last wiring level inductor using patterned plate process | Anil K. Chinthakindi, Douglas D. Coolbaugh, John E. Florkey, Zhong-Xiang He, Anthony K. Stamper +1 more | 2010-07-27 |
| 7759755 | Anti-reflection structures for CMOS image sensors | James W. Adkisson, John J. Ellis-Monaghan, Charles F. Musante | 2010-07-20 |
| 7741698 | Post last wiring level inductor using patterned plate process | Anil K. Chinthakindi, Douglas D. Coolbaugh, John E. Florkey, Zhong-Xiang He, Anthony K. Stamper +1 more | 2010-06-22 |
| 7737528 | Structure and method of forming electrically blown metal fuses for integrated circuits | Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Chao-Kun Hu +3 more | 2010-06-15 |