Issued Patents All Time
Showing 76–100 of 142 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10923401 | Gate cut critical dimension shrink and active gate defect healing using selective deposition | Andrew M. Greene, Marc A. Bergendahl, Alex Joseph Varghese, Yann Mignot, Matthew T. Shoudy +2 more | 2021-02-16 |
| 10903111 | Semiconductor device with linerless contacts | Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy +2 more | 2021-01-26 |
| 10901317 | Extreme ultraviolet (EUV) lithography patterning methods utilizing EUV resist hardening | Benjamin D. Briggs, Michael Rizzolo, Chih-Chao Yang, Lawrence A. Clevenger | 2021-01-26 |
| 10892193 | Controlling active fin height of FinFET device | Yi Song, Veeraraghavan S. Baskar, Jay William Strane | 2021-01-12 |
| 10886169 | Airgap formation in BEOL interconnect structure using sidewall image transfer | Kangguo Cheng, Juntao Li, Yi Song, Peng Xu | 2021-01-05 |
| 10886462 | Encapsulated memory pillars | Ashim Dutta, Jennifer Church, Luciana Meli Thompson | 2021-01-05 |
| 10879107 | Method of forming barrier free contact for metal interconnects | Ashim Dutta, Jennifer Church, Luciana Meli Thompson | 2020-12-29 |
| 10832945 | Techniques to improve critical dimension width and depth uniformity between features with different layout densities | Nicole Saulnier, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Gauri Karve +3 more | 2020-11-10 |
| 10831102 | Photoactive polymer brush materials and EUV patterning using the same | Rudy J. Wojtecki, Dario L. Goldfarb, Daniel P. Sanders, Nelson Felix | 2020-11-10 |
| 10804106 | High temperature ultra-fast annealed soft mask for semiconductor devices | Mona A. Ebrish, Oleg Gluschenkov, Indira Seshadri | 2020-10-13 |
| 10790372 | Direct gate metal cut using selective deposition to protect the gate end line from metal shorts | Andrew M. Greene | 2020-09-29 |
| 10782613 | Polymerizable self-assembled monolayers for use in atomic layer deposition | Rudy J. Wojtecki, Noah Frederick Fine Nathel | 2020-09-22 |
| 10770361 | Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal | Yi Song, Veeraraghavan S. Baskar, Jay William Strane | 2020-09-08 |
| 10768532 | Co-optimization of lithographic and etching processes with complementary post exposure bake by laser annealing | Jing Sha, Nelson Felix, Derren N. Dunn | 2020-09-08 |
| 10755928 | Fabricating electrically nonconductive blocks using a polymer brush and a sequential infiltration synthesis process | Chi-Chun Liu, Kristin Schmidt, Yann Mignot, Martha I. Sanchez, Daniel P. Sanders +1 more | 2020-08-25 |
| 10755926 | Patterning directly on an amorphous silicon hardmask | Abraham Arceo de la Pena, Nelson Felix | 2020-08-25 |
| 10741454 | Boundary protection for CMOS multi-threshold voltage devices | Jing Guo, Nicolas Loubet, Indira Seshadri, Nelson Felix | 2020-08-11 |
| 10734523 | Nanosheet substrate to source/drain isolation | Fee Li Lie, Mona A. Ebrish, Indira Seshadri, Gauri Karve, Lawrence A. Clevenger +2 more | 2020-08-04 |
| 10734234 | Metal cut patterning and etching to minimize interlayer dielectric layer loss | Kisup Chung, Andrew M. Greene, Siva Kanakasabapathy, Indira Seshadri | 2020-08-04 |
| 10727317 | Bottom contact formation for vertical transistor devices | Su Chen Fan, Sivananda K. Kanakasabapathy | 2020-07-28 |
| 10699912 | Damage free hardmask strip | Indira Seshadri | 2020-06-30 |
| 10692755 | Selective deposition of dielectrics on ultra-low k dielectrics | Hosadurga Shobha, Rudy J. Wojtecki, Noel Arellano | 2020-06-23 |
| 10685872 | Electrically isolated contacts in an active region of a semiconductor device | Kangguo Cheng, Peng Xu, Ruilong Xie | 2020-06-16 |
| 10678135 | Surface treatment of titanium containing hardmasks | Dario L. Goldfarb, Indira Seshadri | 2020-06-09 |
| 10665461 | Semiconductor device with multiple threshold voltages | Praveen Joseph, Indira Seshadri | 2020-05-26 |