Issued Patents All Time
Showing 26–50 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8866266 | Silicon nanotube MOSFET | Daniel Tekleab, Hung H. Tran, Jeffrey W. Sleight | 2014-10-21 |
| 8835234 | MOS having a sic/sige alloy stack | Brian J. Greene, Yue Liang, Xiaojun Yu | 2014-09-16 |
| 8803243 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Yue Liang, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha +1 more | 2014-08-12 |
| 8642434 | Structure and method for mobility enhanced MOSFETS with unalloyed silicide | Yaocheng Liu, Oleg Gluschenkov, Judson R. Holt, Renee T. Mo, Kern Rim | 2014-02-04 |
| 8629022 | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same | Sunfei Fang, Yue Liang, Xiaojun Yu, Jun Yuan | 2014-01-14 |
| 8629501 | Stress-generating structure for semiconductor-on-insulator devices | Huilong Zhu, Brian J. Greene, Gregory G. Freeman | 2014-01-14 |
| 8541814 | Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers | Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus | 2013-09-24 |
| 8492802 | Multiple orientation nanowires with gate stack sensors | Xiao Hu Liu, Lidija Sekaric | 2013-07-23 |
| 8492268 | IC having viabar interconnection and related method | Stephen E. Greco, Kia-Seng Low | 2013-07-23 |
| 8476706 | CMOS having a SiC/SiGe alloy stack | Brian J. Greene, Yue Liang, Xiaojun Yu | 2013-07-02 |
| 8466496 | Selective partial gate stack for improved device isolation | Xiaojun Yu, Brian J. Greene, Yue Liang | 2013-06-18 |
| 8453100 | Circuit analysis using transverse buckets | Richard Q. Williams | 2013-05-28 |
| 8445974 | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same | Sunfei Fang, Yue Liang, Xiaojun Yu, Jun Yuan | 2013-05-21 |
| 8429576 | Methods and system for analysis and management of parametric yield | James A. Culp, Paul Chang, Praveen Elakkumanan, Jason D. Hibbeler, Anda C. Mocuta | 2013-04-23 |
| 8418087 | Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance | Shayak Banerjee, James A. Culp, Praveen Elakkumanan, Saibal Mukhopadhyay | 2013-04-09 |
| 8405165 | Field effect transistor having multiple conduction states | David M. Onsongo, David R. Hanson | 2013-03-26 |
| 8368125 | Multiple orientation nanowires with gate stack stressors | Xiao Hu Liu, Lidija Sekaric | 2013-02-05 |
| 8367492 | Multiple Orientation Nanowires with Gate Stack Sensors | Xiao Hu Liu, Lidija Sekaric | 2013-02-05 |
| 8299622 | IC having viabar interconnection and related method | Stephen E. Greco, Kia-Seng Low | 2012-10-30 |
| 8302040 | Compact model methodology for PC landing pad lithographic rounding impact on device performance | Gerald M. Davidson, Paul A. Hyde, Judith H. McCullen, Shreesh Narasimha | 2012-10-30 |
| 8299565 | Semiconductor nanowires having mobility-optimized orientations | Lidija Sekaric, Tymon Barwicz | 2012-10-30 |
| 8299570 | Efuse containing sige stack | Deok-kee Kim, William K. Henson, Chandrasekharan Kothandaraman | 2012-10-30 |
| 8296691 | Methodology for improving device performance prediction from effects of active area corner rounding | Gerald M. Davidson, Paul A. Hyde, Judith H. McCullen, Shreesh Narasimha | 2012-10-23 |
| 8268698 | Formation of improved SOI substrates using bulk semiconductor wafers | William K. Henson, Kern Rim, Hsingjen Wann, Hung Y. Ng | 2012-09-18 |
| 8237150 | Nanowire devices for enhancing mobility through stress engineering | Xiao Hu Liu, Lidija Sekaric | 2012-08-07 |