Issued Patents All Time
Showing 76–100 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7932158 | Formation of improved SOI substrates using bulk semiconductor wafers | William K. Henson, Kern Rim, Hsingjen Wann, Hung Y. Ng | 2011-04-26 |
| 7928571 | Device having dual etch stop liner and reformed silicide layer and related methods | Ying Li, Rajeev Malik, Shreesh Narasimha | 2011-04-19 |
| 7902541 | Semiconductor nanowire with built-in stress | Lidija Sekaric, Xiao Hu Liu | 2011-03-08 |
| 7888197 | Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer | William K. Henson, Yaocheng Liu | 2011-02-15 |
| 7863197 | Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification | Huajie Chen, Judson R. Holt, Qiqing C. Ouyang, Siddhartha Panda | 2011-01-04 |
| 7843024 | Method and structure for improving device performance variation in dual stress liner technology | Brian J. Greene | 2010-11-30 |
| 7838932 | Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon | Ashima B. Chakravarti, Judson R. Holt, Yaocheng Liu, Kern Rim | 2010-11-23 |
| 7838963 | Electrical fuse having a fully silicided fuselink and enhanced flux divergence | William K. Henson, Deok-kee Kim, Chandrasekharan Kothandaraman | 2010-11-23 |
| 7831941 | CA resistance variability prediction methodology | Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Rama N. Singh, Roger Y. Tsai | 2010-11-09 |
| 7818692 | Automated optimization of device structure during circuit design stage | Jason D. Hibbeler, Richard Q. Williams | 2010-10-19 |
| 7812397 | Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof | Changguo Cheng, Brian J. Greene, Jack A. Mandelman, Kern Rim | 2010-10-12 |
| 7791144 | High performance stress-enhance MOSFET and method of manufacture | Ricardo A. Donaton, William K. Henson, Kern Rim | 2010-09-07 |
| 7781800 | Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer | Huajie Chen, Dominic J. Schepis, Henry K. Utomo | 2010-08-24 |
| 7776695 | Semiconductor device structure having low and high performance devices of same conductive type on same substrate | John C. Arnold, Ying Li, Rajeev Malik, Shreesh Narasimha, Siddhartha Panda +2 more | 2010-08-17 |
| 7768041 | Multiple conduction state devices having differently stressed liners | David M. Onsongo | 2010-08-03 |
| 7761278 | Semiconductor device stress modeling methodology | Richard Q. Williams | 2010-07-20 |
| 7759739 | Transistor with dielectric stressor elements | Brian J. Greene, Kern Rim | 2010-07-20 |
| 7750410 | Structure and method to improve channel mobility by gate electrode stress modification | Michael P. Belyansky, Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov | 2010-07-06 |
| 7745277 | MOSFET performance improvement using deformation in SOI structure | Omer H. Dokumaci | 2010-06-29 |
| 7741186 | Creating increased mobility in a bipolar device | Gregory G. Freeman, Marwan H. Khater | 2010-06-22 |
| 7737014 | Reduction of boron diffusivity in pFETs | Frederick Buehrer, Bruce B. Doris, Hsiang-Jen Huang, Haining Yang | 2010-06-15 |
| 7732288 | Method for fabricating a semiconductor structure | Huilong Zhu, Lawrence A. Clevenger, Omer H. Dokumaci, Oleg Gluschenkov, Kaushik A. Kumar +1 more | 2010-06-08 |
| 7732270 | Device having enhanced stress state and related methods | Ying Li, Rajeev Malik, Shreesh Narasimha, Haining Yang, Huilong Zhu | 2010-06-08 |
| 7709910 | Semiconductor structure for low parasitic gate capacitance | William K. Henson, Paul Chang, Ricardo A. Donaton, Yaocheng Liu, Shreesh Narasimha +1 more | 2010-05-04 |
| 7705345 | High performance strained silicon FinFETs device and method for forming same | Stephen W. Bedell, Kevin K. Chan, Silke H. Christianson, Jack O. Chu, Anthony G. Domenicucci +4 more | 2010-04-27 |