Issued Patents All Time
Showing 126–150 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7504697 | Rotational shear stress for charge carrier mobility modification | — | 2009-03-17 |
| 7495291 | Strained dislocation-free channels for CMOS and method of manufacture | Omer H. Dokumaci | 2009-02-24 |
| 7488658 | Stressed semiconductor device structures having granular semiconductor material | Bruce B. Doris, Michael P. Belyansky, Diane C. Boyd, Oleg Gluschenkov | 2009-02-10 |
| 7485519 | After gate fabrication of field effect transistor having tensile and compressive regions | William K. Henson, Yaocheng Liu | 2009-02-03 |
| 7476938 | Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress | Brian J. Greene, Kern Rim | 2009-01-13 |
| 7473594 | Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon | Ashima B. Chakravarti, Judson R. Holt, Yaocheng Liu, Kern Rim | 2009-01-06 |
| 7468538 | Strained silicon on a SiGe on SOI substrate | Kangguo Cheng | 2008-12-23 |
| 7462916 | Semiconductor devices having torsional stresses | Richard Q. Williams, John J. Ellis-Monaghan, Shreesh Narasimha, Edward J. Nowak, John J. Pekarik | 2008-12-09 |
| 7462522 | Method and structure for improving device performance variation in dual stress liner technology | Brian J. Greene | 2008-12-09 |
| 7452784 | Formation of improved SOI substrates using bulk semiconductor wafers | William K. Henson, Kern Rim, Hsingjen Wann, Hung Y. Ng | 2008-11-18 |
| 7449378 | Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regions | Brian J. Greene | 2008-11-11 |
| 7446062 | Device having dual etch stop liner and reformed silicide layer and related methods | Ying Li, Rajeev Malik, Shreesh Narasimha | 2008-11-04 |
| 7446395 | Device having dual etch stop liner and protective layer | Ying Li, Rajeev Malik, Shreesh Narasimha | 2008-11-04 |
| 7446350 | Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer | Huajie Chen, Dominic J. Schepis, Henry K. Utomo | 2008-11-04 |
| 7439123 | Low resistance contact semiconductor device structure | William K. Henson | 2008-10-21 |
| 7436029 | High performance CMOS device structures and method of manufacture | Bruce B. Doris, Suk Hoon Ku | 2008-10-14 |
| 7410846 | Method for reduced N+ diffusion in strained Si on SiGe substrate | Omer H. Dokumaci | 2008-08-12 |
| 7405436 | Stressed field effect transistors on hybrid orientation substrate | Judson R. Holt, Meikei Ieong, Oiging C. Ouyang, Siddhartha Panda | 2008-07-29 |
| 7397081 | Sidewall semiconductor transistors | Huilong Zhu, Lawrence A. Clevenger, Omer H. Dokumaci, Kaushik A. Kumar, Carl Radens | 2008-07-08 |
| 7396714 | Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Huajie Chen, Oleg Gluschenkov, An Steegen, Haining Yang | 2008-07-08 |
| 7388259 | Strained finFET CMOS device structures | Bruce B. Doris, Meikei Ieong, Jack A. Mandelman | 2008-06-17 |
| 7374987 | Stress inducing spacers | Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman, Xavier Baie | 2008-05-20 |
| 7361973 | Embedded stressed nitride liners for CMOS performance improvement | Omer H. Dokumaci | 2008-04-22 |
| 7358551 | Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions | Brian J. Greene | 2008-04-15 |
| 7348635 | Device having enhanced stress state and related methods | Ying Li, Rajeev Malik, Shreesh Narasimha, Haining Yang, Huilong Zhu | 2008-03-25 |