Issued Patents All Time
Showing 176–200 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7135724 | Structure and method for making strained channel field effect transistor using sacrificial spacer | Huajie Chen, Sang-Hyun Oh, Siddhartha Panda, Werner Rausch, Tsutomu Sato +1 more | 2006-11-14 |
| 7129130 | Out of the box vertical transistor for eDRAM on SOI | James W. Adkisson, Gary B. Bronner, Ramachandra Divakaruni, Carl Radens | 2006-10-31 |
| 7122849 | Stressed semiconductor device structures having granular semiconductor material | Bruce B. Doris, Michael P. Belyansky, Diane C. Boyd, Oleg Gluschenkov | 2006-10-17 |
| 7123529 | Sense amplifier including multiple conduction state field effect transistor | David R. Hanson, David M. Onsongo | 2006-10-17 |
| 7102205 | Bipolar transistor with extrinsic stress layer | Gregory G. Freeman, Marwan H. Khater | 2006-09-05 |
| 7102914 | Gate controlled floating well vertical MOSFET | Xiangdong Chen, Geng Wang | 2006-09-05 |
| 7091563 | Method and structure for improved MOSFETs using poly/silicide gate height control | Omer H. Dokumaci | 2006-08-15 |
| 7060539 | Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby | Omer H. Dokumaci | 2006-06-13 |
| 7045873 | Dynamic threshold voltage MOSFET on SOI | Xiangdong Chen, Geng Wang | 2006-05-16 |
| 7037770 | Method of manufacturing strained dislocation-free channels for CMOS | Omer H. Dokumaci | 2006-05-02 |
| 7029964 | Method of manufacturing a strained silicon on a SiGe on SOI substrate | Kangguo Cheng | 2006-04-18 |
| 7018551 | Pull-back method of forming fins in FinFets | Jochen Beintner, Yujun Li, Kenneth T. Settlemyer, Jr. | 2006-03-28 |
| 7009237 | Out of the box vertical transistor for eDRAM on SOI | James W. Adkisson, Gary B. Bronner, Ramachandra Divakaruni, Carl Radens | 2006-03-07 |
| 7002209 | MOSFET structure with high mechanical stress in the channel | Xiangdong Chen, Oleg Gluschenkov, Brian J. Greene, Kern Rim, Haining Yang | 2006-02-21 |
| 6979851 | Structure and method of vertical transistor DRAM cell having a low leakage buried strap | Jack A. Mandelman, Carl Radens | 2005-12-27 |
| 6977194 | Structure and method to improve channel mobility by gate electrode stress modification | Michael P. Belyansky, Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov | 2005-12-20 |
| 6974981 | Isolation structures for imposing stress patterns | Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman | 2005-12-13 |
| 6972461 | Channel MOSFET with strained silicon channel on strained SiGe | Xiangdong Chen, Geng Wang, Huilong Zhu | 2005-12-06 |
| 6967384 | Structure and method for ultra-small grain size polysilicon | Jochen Beintner | 2005-11-22 |
| 6930004 | Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling | Geng Wang, Kevin McStay, Mary E. Weybright, Yujun Li | 2005-08-16 |
| 6906360 | Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions | Huajie Chen, Omer Dokumaci, Haining Yang | 2005-06-14 |
| 6891192 | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Huajie Chen, Oleg Gluschenkov, An Steegen, Haining Yang | 2005-05-10 |
| 6890808 | Method and structure for improved MOSFETs using poly/silicide gate height control | Omer H. Dokumaci | 2005-05-10 |
| 6887751 | MOSFET performance improvement using deformation in SOI structure | Omer H. Dokumaci | 2005-05-03 |
| 6884667 | Field effect transistor with stressed channel and method for making same | Bruce B. Doris, Xavier Baie, Jack A. Mandelman, Devendra K. Sadana, Dominic J. Schepis | 2005-04-26 |