Issued Patents All Time
Showing 151–175 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7348638 | Rotational shear stress for charge carrier mobility modification | — | 2008-03-25 |
| 7345329 | Method for reduced N+ diffusion in strained Si on SiGe substrate | Omer H. Dokumaci | 2008-03-18 |
| 7342266 | Field effect transistors with dielectric source drain halo regions and reduced miller capacitance | Michael P. Belyansky, Oleg Gluschenkov | 2008-03-11 |
| 7337420 | Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models | Donald L. Jordan, Judith H. McCullen, David M. Onsongo, Tina Wagner, Richard Q. Williams | 2008-02-26 |
| 7329941 | Creating increased mobility in a bipolar device | Gregory G. Freeman, Marwan H. Khater | 2008-02-12 |
| 7312134 | Dual stressed SOI substrates | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Huilong Zhu | 2007-12-25 |
| 7306983 | Method for forming dual etch stop liner and protective layer in a semiconductor device | Ying Li, Rajeev Malik, Shreesh Narasimha | 2007-12-11 |
| 7303949 | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture | Huajie Chen, Omer H. Dokumaci | 2007-12-04 |
| 7297583 | Method of making strained channel CMOS transistors having lattice-mismatched epitaxial | Huajie Chen, Omer Dokumaci, Haining Yang | 2007-11-20 |
| 7297601 | Method for reduced N+ diffusion in strained Si on SiGe substrate | Omer H. Dokumaci | 2007-11-20 |
| 7291528 | Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Huajie Chen, Oleg Gluschenkov, An Steegen, Haining Yang | 2007-11-06 |
| 7279746 | High performance CMOS device structures and method of manufacture | Bruce B. Doris, Suk Hoon Ku | 2007-10-09 |
| 7274084 | Enhanced PFET using shear stress | — | 2007-09-25 |
| 7262087 | Dual stressed SOI substrates | Bruce B. Doris, Oleg Gluschenkov, Omer H. Dokumaci, Huilong Zhu | 2007-08-28 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture | Omer H. Dokumaci, Oleg Gluschenkov | 2007-07-24 |
| 7242239 | Programming and determining state of electrical fuse using field effect transistor having multiple conduction states | David R. Hanson, Gregory J. Fredeman, David M. Onsongo | 2007-07-10 |
| 7224021 | MOSFET with high angle sidewall gate and contacts for reduced miller capacitance | Lawrence A. Clevenger, Omer H. Dokumaci, Kaushik A. Kumar, Huilong Zhu | 2007-05-29 |
| 7223994 | Strained Si on multiple materials for bulk or SOI substrates | Omer H. Dokumaci, Oleg Gluschenkov, Huilong Zhu | 2007-05-29 |
| 7221024 | Transistor having dielectric stressor elements for applying in-plane shear stress | Brian J. Green, Kern Rim | 2007-05-22 |
| 7202513 | Stress engineering using dual pad nitride with selective SOI device architecture | William K. Henson, Kern Rim, William C. Wille | 2007-04-10 |
| 7198995 | Strained finFETs and method of manufacture | Omer H. Dokumaci, Oleg Gluschenkov | 2007-04-03 |
| 7195972 | Trench capacitor DRAM cell using buried oxide as array top oxide | Ramachandra Divakaruni, Deok-kee Kim | 2007-03-27 |
| 7176481 | In situ doped embedded sige extension and source/drain for enhanced PFET performance | Huajie Chen, Siddhartha Panda, Sang-Hyun Oh, Henry K. Utomo, Werner Rausch | 2007-02-13 |
| 7170126 | Structure of vertical strained silicon devices | Kangguo Cheng, Rama Divakaruni, Oleg Gluschenkov | 2007-01-30 |
| 7144767 | NFETs using gate induced stress modulation | Omer H. Dokumaci, Oleg Gluschenkov | 2006-12-05 |