Issued Patents All Time
Showing 201–225 of 230 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6881635 | Strained silicon NMOS devices with embedded source/drain | Effendi Leobandung, Anda C. Mocuta, Haining Yang, Huilong Zhu | 2005-04-19 |
| 6878978 | CMOS performance enhancement using localized voids and extended defects | Omer H. Dokumaci, Suryanarayan G. Hegde | 2005-04-12 |
| 6872620 | Trench capacitors with reduced polysilicon stress | Rajarao Jammy, Jack A. Mandelman | 2005-03-29 |
| 6873010 | High performance logic and high density embedded dram with borderless contact and antispacer | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Rajarao Jammy, Jack A. Mandelman | 2005-03-29 |
| 6872641 | Strained silicon on relaxed sige film with uniform misfit dislocation density | Omer H. Dokumaci | 2005-03-29 |
| 6869866 | Silicide proximity structures for CMOS device performance improvements | Omer H. Dokumaci, Rajesh Rengarajan, An Steegen | 2005-03-22 |
| 6858488 | CMOS performance enhancement using localized voids and extended defects | Omer H. Dokumaci, Suryanarayan G. Hegde | 2005-02-22 |
| 6833305 | Vertical DRAM punchthrough stop self-aligned to storage trench | Jack A. Mandelman, Ramachandra Divakaruni | 2004-12-21 |
| 6825529 | Stress inducing spacers | Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman, Xavier Baie | 2004-11-30 |
| 6803270 | CMOS performance enhancement using localized voids and extended defects | Omer H. Dokumachi, Suryanarayan G. Hegde | 2004-10-12 |
| 6787838 | Trench capacitor DRAM cell using buried oxide as array top oxide | Ramachandra Divakaruni, Deok-kee Kim | 2004-09-07 |
| 6777737 | Vertical DRAM punchthrough stop self-aligned to storage trench | Jack A. Mandelman, Ramachandra Divakaruni | 2004-08-17 |
| 6740920 | Vertical MOSFET with horizontally graded channel doping | Kil-Ho Lee, Jack A. Mandelman, Kevin McStay, Rajesh Rengarajan | 2004-05-25 |
| 6734056 | Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell | Jack A. Mandelman | 2004-05-11 |
| 6724031 | Method for preventing strap-to-strap punch through in vertical DRAMs | Hiroyuki Akatsu, Ramachandra Divakaruni, Jack A. Mandelman, Carl Radens | 2004-04-20 |
| 6717216 | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device | Bruce B. Doris, Xavier Baie, Jack A. Mandelman, Devendra K. Sadana, Dominic J. Schepis | 2004-04-06 |
| 6709926 | High performance logic and high density embedded dram with borderless contact and antispacer | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Rajarao Jammy, Jack A. Mandelman | 2004-03-23 |
| 6707095 | Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation | Jack A. Mandelman, Carl Radens | 2004-03-16 |
| 6703274 | Buried strap with limited outdiffusion and vertical transistor DRAM | Ramachandra Divakaruni, Jack A. Mandelman, Raymond Van Roijen | 2004-03-09 |
| 6653678 | Reduction of polysilicon stress in trench capacitors | Rajarao Jammy, Jack A. Mandelman | 2003-11-25 |
| 6573585 | Electrically blowable fuse with reduced cross-sectional area | Kenneth C. Arndt, Louis L. Hsu, Jack A. Mandelman, Carl Radens | 2003-06-03 |
| 6573561 | Vertical MOSFET with asymmetrically graded channel doping | Ramachandra Divakaruni, Jack A. Mandelman, Kevin McStay | 2003-06-03 |
| 6548358 | Electrically blowable fuse with reduced cross-sectional area | Kenneth C. Arndt, Louis L. Hsu, Jack A. Mandelman, Carl Radens | 2003-04-15 |
| 6534824 | Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell | Jack A. Mandelman | 2003-03-18 |
| 6417572 | Process for producing metal interconnections and product produced thereby | Ronald G. Filippi, Robert Rosenberg, Thomas M. Shaw, Timothy D. Sullivan, Richard A. Wachnik | 2002-07-09 |