Issued Patents 2020
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879214 | Die stack structure and method of fabricating the same | Yi-Hsiu Chen, Yung-Lung Chen | 2020-12-29 |
| 10872874 | Bonding apparatus and method of bonding substrates | Chen-Hua Yu, Ebin Liao | 2020-12-22 |
| 10867831 | Method and apparatus for bonding semiconductor devices | Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao | 2020-12-15 |
| 10867985 | Method and structure of three-dimensional chip stacking | Chen-Hua Yu, Yung-Chi Lin | 2020-12-15 |
| 10867963 | Die stack structure and method of fabricating the same | Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu | 2020-12-15 |
| 10867943 | Die structure, die stack structure and method of fabricating the same | Yi-Hsiu Chen, Tsang-Jiuh Wu, Tung-Hsien Wu | 2020-12-15 |
| 10854567 | 3D packages and methods for forming the same | Shang-Yun Hou, Sao-Ling Chiu, Ping-Kang Huang, Wen-Hsin Wei, Shin-Puu Jeng +1 more | 2020-12-01 |
| 10854574 | Forming metal bonds with recesses | Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh | 2020-12-01 |
| 10847414 | Embedded 3D interposer structure | Ying-Ching Shih, Jing-Cheng Lin, Shin-Puu Jeng, Chen-Hua Yu | 2020-11-24 |
| 10811374 | Interconnect structure and method of forming same | Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin +2 more | 2020-10-20 |
| 10797031 | Semiconductor package | Yu-Kuang Liao, Cheng-Chun Tsai, Chen-Hua Yu, Fang Chen, Ping-Jung Wu | 2020-10-06 |
| 10784162 | Method of making a semiconductor component having through-silicon vias | Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang +4 more | 2020-09-22 |
| 10748803 | Method and apparatus for bonding semiconductor devices | Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao | 2020-08-18 |
| 10727294 | Semiconductor devices, methods of manufacture thereof, and capacitors | Shin-Puu Jeng, Ebin Liao | 2020-07-28 |
| 10714423 | Through via structure and method | Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu | 2020-07-14 |
| 10692764 | Alignment marks in substrate having through-substrate via (TSV) | Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Shin-Puu Jeng | 2020-06-23 |
| 10685935 | Forming metal bonds with recesses | Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh | 2020-06-16 |
| 10672737 | Three-dimensional integrated circuit structure and method of manufacturing the same | Yi-Hsiu Chen, Ebin Liao, Hong-Ye Shih, Jia-Ling Ko | 2020-06-02 |
| 10665582 | Method of manufacturing semiconductor package structure | Yi-Hsiu Chen, Chen-Hua Yu, Ming-Fa Chen | 2020-05-26 |
| 10622302 | Via for semiconductor device connection and methods of forming the same | Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Tsang-Jiuh Wu, Der-Chyang Yeh +1 more | 2020-04-14 |
| 10566237 | Profile of through via protrusion in 3DIC interconnect | Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Ku-Feng Yang +3 more | 2020-02-18 |
| 10535586 | Robust through-silicon-via structure | Yung-Chi Lin, Tsang-Jiuh Wu | 2020-01-14 |
| 10529679 | 3D packages and methods for forming the same | Shang-Yun Hou, Sao-Ling Chiu, Ping-Kang Huang, Wen-Hsin Wei, Shin-Puu Jeng +1 more | 2020-01-07 |