Issued Patents All Time
Showing 26–50 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11088079 | Package structure having line connected via portions | Chih-Kai Cheng, Tsung-Shu Lin, Tsung-Yu Chen, Wen-Hsin Wei | 2021-08-10 |
| 11069657 | Chip package having die structures of different heights and method of forming same | Wen-Hsin Wei, Shang-Yun Hou | 2021-07-20 |
| 11069539 | 3D packages and methods for forming the same | Tzu-Wei Chiu, Cheng-Hsien Hsieh, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng | 2021-07-20 |
| 11062971 | Package structure and method and equipment for forming the same | Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei | 2021-07-13 |
| 10985137 | Stacked integrated circuit structure and method of forming | Wei-Ming Chen, Shang-Yun Hou, Wen-Hsin Wei | 2021-04-20 |
| 10964667 | Stacked integrated circuit structure and method of forming | Wei-Ming Chen, Shang-Yun Hou, Wen-Hsin Wei | 2021-03-30 |
| 10923431 | Method for forming a 3D IC architecture including forming a first die on a first side of a first interconnect structure and a second die in an opening formed in a second side | Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun-Ren Lai, Yung-Chi Lin | 2021-02-16 |
| 10770365 | Package structures and methods of forming the same | Chen-Hua Yu, Jing-Cheng Lin, Szu-Wei Lu, Shang-Yun Hou, Wen-Hsin Wei +2 more | 2020-09-08 |
| 10734295 | Interposer test structures and methods | Tzuan-Horng Liu, Chen-Hua Yu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou +1 more | 2020-08-04 |
| 10665474 | 3D packages and methods for forming the same | Tzu-Wei Chiu, Cheng-Hsien Hsieh, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng | 2020-05-26 |
| 10663512 | Testing of semiconductor chips with microbumps | Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang | 2020-05-26 |
| 10535633 | Chip package having die structures of different heights and method of forming same | Wen-Hsin Wei, Shang-Yun Hou | 2020-01-14 |
| 10515906 | Forming large chips through stitching | Wen-Hsin Wei, Shang-Yun Hou, Weiming Chris Chen | 2019-12-24 |
| RE47709 | Forming grounded through-silicon vias in a semiconductor substrate | Chi-Chun Hsieh, Wei-Cheng Wu, Hsiao-Tsung Yen, Shang-Yun Hou, Shin-Puu Jeng | 2019-11-05 |
| 10319699 | Chip package having die structures of different heights | Wen-Hsin Wei, Chi-Hsi Wu, Chen-Hua Yu, Shang-Yun Hou, Weiming Chris Chen | 2019-06-11 |
| 10297550 | 3D IC architecture with interposer and interconnect structure for bonding dies | Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun-Ren Lai, Yung-Chi Lin | 2019-05-21 |
| 10269584 | 3D packages and methods for forming the same | Tzu-Wei Chiu, Cheng-Hsien Hsieh, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng | 2019-04-23 |
| 10262939 | Configurable routing for packaging applications | Chung-Yu Lu, Shin-Puu Jeng, Shang-Yun Hou, Tzuan-Horng Liu, Shih-Wen Huang +1 more | 2019-04-16 |
| 10175294 | Testing of semiconductor chips with microbumps | Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang | 2019-01-08 |
| 10163856 | Stacked integrated circuit structure and method of forming | Wei-Ming Chen, Shang-Yun Hou, Wen-Hsin Wei | 2018-12-25 |
| 10163853 | Formation method of chip package | Wen-Hsin Wei, Chi-Hsi Wu, Chen-Hua Yu, Shang-Yun Hou, Wei-Ming Chen | 2018-12-25 |
| 10153222 | Package structures and methods of forming the same | Chen-Hua Yu, Jing-Cheng Lin, Szu-Wei Lu, Shang-Yun Hou, Wen-Hsin Wei +2 more | 2018-12-11 |
| 10090213 | Interposer test structures and methods | Tzuan-Horng Liu, Chen-Hua Yu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou +1 more | 2018-10-02 |
| 10014252 | Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors | Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin +2 more | 2018-07-03 |
| 9978637 | Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs) | Tzuan-Horng Liu, Shih-Wen Huang, Chung-Yu Lu, Shang-Yun Hou, Shin-Puu Jeng | 2018-05-22 |