Issued Patents All Time
Showing 51–75 of 134 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8329598 | Sacrificial nitride and gate replacement | Chungho Lee, Hiroyuki Kinoshita, Huaqiang Wu, Fred Cheung | 2012-12-11 |
| 8319266 | Etch stop layer for memory cell reliability improvement | Hiroyuki Kinoshita, Angela T. Hui, Hsiao-Han Thio, Minh Van Ngo, Hiroyuki Ogawa | 2012-11-27 |
| 8283718 | Integrated circuit system with metal and semi-conducting gate | Angela T. Hui, Mark S. Chang, Scott A. Bell | 2012-10-09 |
| 8208296 | Apparatus and method for extended nitride layer in a flash memory | Timothy Thurgate, Shenqing Fang, Youseok Suh | 2012-06-26 |
| 8183623 | Dual charge storage node memory device and methods for fabricating such device | Chungho Lee, Hiroyuki Kinoshita, Amol Joshi, Kyunghoon Min, Chi Chang | 2012-05-22 |
| 8144522 | Erasing flash memory using adaptive drain and/or gate bias | Wei Zheng | 2012-03-27 |
| 8143661 | Memory cell system with charge trap | Shenqing Fang, Rinji Sugino, Jayendra D. Bhakta, Takashi Orimoto, Hiroyuki Nansei +8 more | 2012-03-27 |
| 8133801 | Method for forming a semiconducting layer with improved gap filling properties | Rinji Sugino, Yider Wu, Minh Van Ngo, Jeffrey S. Glick | 2012-03-13 |
| 8114736 | Integrated circuit system with memory system | Simon S. Chan, Hidehiko Shiraiwa, Angela T. Hui | 2012-02-14 |
| 8076712 | Semiconductor memory comprising dual charge storage nodes and methods for its fabrication | Chungho Lee, Ashot Melik-Martirosian, Wei Zheng, Timothy Thurgate, Chi Chang +2 more | 2011-12-13 |
| 8012830 | ORO and ORPRO with bit line trench to suppress transport program disturb | Ning Cheng, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee +3 more | 2011-09-06 |
| 7998846 | 3-D integrated circuit system and method | Eunha Kim, Jeremy A. Wahl, Shenqing Fang, Youseok Suh, Yi Ma +2 more | 2011-08-16 |
| 7995386 | Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb | Yuji Mizuguchi, Mark Randolph, Darlene Hamilton, Yi He, Zhizheng Liu +9 more | 2011-08-09 |
| 7981745 | Sacrificial nitride and gate replacement | Chungho Lee, Hiroyuki Kinoshita, Huaqiang Wu, Fred Cheung | 2011-07-19 |
| 7952938 | Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory | Gulzar Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate +2 more | 2011-05-31 |
| 7943980 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications | Shenqing Fang, Tim Thurgate, Youseok Suh, Allison Holbrook | 2011-05-17 |
| 7915123 | Dual charge storage node memory device and methods for fabricating such device | Chungho Lee, Hiroyuki Kinoshita, Amol Joshi, Kyunghoon Min, Chi Chang | 2011-03-29 |
| 7906395 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications | Shenqing Fang, Tim Thurgate, Youseok Suh, Allison Holbrook | 2011-03-15 |
| 7907448 | Scaled down select gates of NAND flash memory cell strings and method of forming same | Youseok Suh, Shenqing Fang | 2011-03-15 |
| 7906807 | Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics | Ning Cheng, Calvin T. Gabriel, Angela T. Hui, Lei Xue, Harpreet Sachar +3 more | 2011-03-15 |
| 7851306 | Method for forming a flash memory device with straight word lines | Shenqing Fang, Hiroyuki Ogawa, Pavel Fastenko, Kazuhiro Mizutani, Zhigang Wang | 2010-12-14 |
| 7842618 | System and method for improving mesa width in a semiconductor device | Unsoon Kim, Angela T. Hui, Yider Wu, Hiroyuki Kinoshita | 2010-11-30 |
| 7803680 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications | Shenging Fang, Tim Thurgate, Youseok Suh, Allison Holbrook | 2010-09-28 |
| 7776688 | Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics | Ning Cheng, Calvin T. Gabriel, Angela T. Hui, Lei Xue, Harpreet Sachar +3 more | 2010-08-17 |
| 7778088 | Erasing flash memory using adaptive drain and/or gate bias | Wei Zheng | 2010-08-17 |