Issued Patents All Time
Showing 76–100 of 134 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7767517 | Semiconductor memory comprising dual charge storage nodes and methods for its fabrication | Chungho Lee, Ashot Melik-Martirosian, Wei Zheng, Timothy Thurgate, Chi Chang +2 more | 2010-08-03 |
| 7746705 | Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory | Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Timothy Thurgate +2 more | 2010-06-29 |
| 7746698 | Programming in memory devices using source bitline voltage bias | Zhizheng Liu, An-Chung Chen, Wei Zheng, Sung-Yong Chung, Gulzar Ahmed Kathawala +1 more | 2010-06-29 |
| 7696038 | Methods for fabricating flash memory devices | Ning Cheng, Hiroyuki Kinoshita, Timothy Thurgate, Wei Zheng, Ashot Melik-Martirosian +2 more | 2010-04-13 |
| 7679129 | System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device | Angela T. Hui, Unsoon Kim, Hiroyuki Kinoshita | 2010-03-16 |
| 7675104 | Integrated circuit memory system employing silicon rich layers | Amol Joshi, Harpreet Sachar, Youseok Suh, Shenqing Fang, Chih-Yuh Yang +6 more | 2010-03-09 |
| 7666739 | Methods for fabricating a split charge storage node semiconductor memory | Chungho Lee, Ashot Melik-Martirosian, Hiroyuki Kinoshita, Sugimo Rinji, Wei Zheng | 2010-02-23 |
| 7659569 | Work function engineering for FN erase of a memory device with multiple charge storage elements in an undercut region | Wei Zheng, Sung-Yong Chung, Ashot Melik-Martirosian | 2010-02-09 |
| 7632749 | Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer | Hiroyuki Ogawa, Yider Wu, Nian Yang, Yu Sun | 2009-12-15 |
| 7622389 | Selective contact formation using masking and resist patterning techniques | Kyunghoon Min, Mark S. Chang, Ning Cheng, Brian Osborn, Kevin Song +3 more | 2009-11-24 |
| 7599228 | Flash memory device having increased over-erase correction efficiency and robustness against device variations | Qiang Lu, Kazuhiro Mizutani, Sung-chul Lee, Sheung-Hee Park, Ming Sang Kwan | 2009-10-06 |
| 7564091 | Memory device and methods for its fabrication | Chungho Lee, Ashot Melik-Martirosian, Hiroyuki Kinoshita, Amol Joshi, Meng Ding | 2009-07-21 |
| 7489560 | Reduction of leakage current and program disturbs in flash memory devices | Timothy Thurgate | 2009-02-10 |
| 7488657 | Method and system for forming straight word lines in a flash memory array | Shenqing Fang, Hiroyuki Ogawa, Pavel Fastenko, Kazuhiro Mizutani, Zhigang Wang | 2009-02-10 |
| 7439141 | Shallow trench isolation approach for improved STI corner rounding | Unsoon Kim, Yu Sun, Hiroyuki Kinoshita, Harpreet Sachar, Mark S. Chang | 2008-10-21 |
| 7432156 | Memory device and methods for its fabrication | Chungho Lee, Ashot Melik-Martirosian, Hiroyuki Kinoshita, Amol Joshi, Meng Ding | 2008-10-07 |
| 7382650 | Method and apparatus for sector erase operation in a flash memory array | — | 2008-06-03 |
| 7323726 | Method and apparatus for coupling to a common line in an array | Yu Sun | 2008-01-29 |
| 7301193 | Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell | Shenqing Fang, Timothy Thurgate, Richard Fastow, Angela T. Hui, Kazuhiro Mizutani +4 more | 2007-11-27 |
| 7217964 | Method and apparatus for coupling to a source line in a memory device | Richard Fastow | 2007-05-15 |
| 7170130 | Memory cell with reduced DIBL and Vss resistance | Shenqing Fang, Pavel Fastenko, Zhigang Wang | 2007-01-30 |
| 7151027 | Method and device for reducing interface area of a memory device | Hiroyuki Ogawa, Yider Wu, Yu Sun | 2006-12-19 |
| 7151028 | Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability | Shenqing Fang, Rinji Sugino, Zhigang Wang, Kazuhiro Mizutani, Pavel Fastenko | 2006-12-19 |
| 7029975 | Method and apparatus for eliminating word line bending by source side implantation | Shenqing Fang, Pavel Fastenko, Kazuhiro Mizutani | 2006-04-18 |
| 7019366 | Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance | Nian Yang, Hiroyuki Ogawa, Yider Wu, Yu Sun | 2006-03-28 |