Issued Patents All Time
Showing 101–120 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10020255 | Integration of super via structure in BEOL | Ruqiang Bao, Joe Lee, Hosadurga Shobha, Junli Wang, Yongan Xu | 2018-07-10 |
| 10020254 | Integration of super via structure in BEOL | Ruqiang Bao, Joe Lee, Hosadurga Shobha, Junli Wang, Yongan Xu | 2018-07-10 |
| 9984919 | Inverted damascene interconnect structures | Xunyuan Zhang, Chanro Park, Yongan Xu, Peng Xu | 2018-05-29 |
| 9916986 | Single or mutli block mask management for spacer height and defect reduction for BEOL | Benjamin D. Briggs, Lawrence A. Clevenger | 2018-03-13 |
| 9905478 | Co-integration of tensile silicon and compressive silicon germanium | Nicolas Loubet, Pierre Morin | 2018-02-27 |
| 9859426 | Semiconductor device including optimized elastic strain buffer | Nicolas Loubet, Pierre Morin | 2018-01-02 |
| 9837351 | Avoiding gate metal via shorting to source or drain contacts | Victor Chan, Xuefeng Liu, Yongan Xu | 2017-12-05 |
| 9779944 | Method and structure for cut material selection | Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson Felix, Sivananda K. Kanakasabapathy +3 more | 2017-10-03 |
| 9768113 | Self aligned via in integrated circuit | Yannick Feurprier, Joe Lee, Lars Liebmann, Terry A. Spooner, Douglas M. Trickett +1 more | 2017-09-19 |
| 9679899 | Co-integration of tensile silicon and compressive silicon germanium | Nicolas Loubet, Pierre Morin | 2017-06-13 |
| 9576852 | Integrated circuits with self aligned contacts and methods of manufacturing the same | Ming He, Seowoo Nam, Jim Kelly, Raghuveer Patlotta, Theodorus E. Standaert | 2017-02-21 |
| 9508560 | SiARC removal with plasma etch and fluorinated wet chemical solution combination | Brown C. Peethala, Shariq Siddiqui | 2016-11-29 |
| 9490168 | Via formation using sidewall image transfer process to define lateral dimension | Shyng-Tsong Chen, Cheng Chi, Chi-Chun Liu, Sylvie Mignot, Hosadurga Shobha +3 more | 2016-11-08 |
| 9466563 | Interconnect structure for an integrated circuit and method of fabricating an interconnect structure | Terry A. Spooner, James J. Kelly | 2016-10-11 |
| 9390967 | Method for residue-free block pattern transfer onto metal interconnects for air gap formation | Joe Lee, Brown C. Peethala | 2016-07-12 |
| 9385078 | Self aligned via in integrated circuit | Yannick Feurprier, Joe Lee, Lars Liebmann, Terry A. Spooner, Douglas M. Trickett +1 more | 2016-07-05 |
| 9373582 | Self aligned via in integrated circuit | Yannick Feurprier, Joe Lee, Lars Liebmann, Terry A. Spooner, Douglas M. Trickett +1 more | 2016-06-21 |
| 9252051 | Method for top oxide rounding with protection of patterned features | Joe Lee, Douglas M. Trickett | 2016-02-02 |
| 9214429 | Trench interconnect having reduced fringe capacitance | John H. Zhang, Hsueh-Chung Chen, Lawrence A. Clevenger, Carl Radens, Richard S. Wise +2 more | 2015-12-15 |
| 8927442 | SiCOH hardmask with graded transition layers | Matthew S. Angyal, Yannick Loquet, Son V. Nguyen, Muthumanickam Sankarapandian, Hosadurga Shobha | 2015-01-06 |