Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8643119 | Substantially L-shaped silicide for contact | Zhijiong Luo, Huilong Zhu, Yung Fu Chong, Hung Y. Ng, Kern Rim | 2014-02-04 |
| 8482075 | Structure and method for manufacturing asymmetric devices | Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Robert R. Robison | 2013-07-09 |
| 8232151 | Structure and method for manufacturing asymmetric devices | Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Robert R. Robison | 2012-07-31 |
| 8034692 | Structure and method for manufacturing asymmetric devices | Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Robert R. Robison | 2011-10-11 |
| 8017483 | Method of creating asymmetric field-effect-transistors | Gregory G. Freeman, Shreesh Narasimha, Ning Su, Hasan M. Nayfeh, Werner Rausch +1 more | 2011-09-13 |
| 7960798 | Structure and method to form multilayer embedded stressors | Zhijiong Luo, Ricky S. Amos, Henry K. Utomo | 2011-06-14 |
| 7785950 | Dual stress memory technique method and related structure | Sunfei Fang, Jun Jung Kim, Zhijiong Luo, Hung Y. Ng, Young Way Teh | 2010-08-31 |
| 7618866 | Structure and method to form multilayer embedded stressors | Zhijiong Luo, Ricky S. Amos, Henry K. Utomo | 2009-11-17 |
| 7473608 | N-channel MOSFETs comprising dual stressors, and methods for forming the same | Jinghong Li, Yaocheng Liu, Zhijiong Luo, Anita Madan | 2009-01-06 |
| 7442618 | Method to engineer etch profiles in Si substrate for advanced semiconductor devices | Yung Fu Chong, Brian J. Greene, Siddhartha Panda | 2008-10-28 |
| 7442619 | Method of forming substantially L-shaped silicide contact for a semiconductor device | Zhijiong Luo, Huilong Zhu, Yung Fu Chong, Hung Y. Ng, Kern Rim | 2008-10-28 |
| 7279758 | N-channel MOSFETs comprising dual stressors, and methods for forming the same | Jinghong Li, Yaocheng Liu, Zhijiong Luo, Anita Madan | 2007-10-09 |
| 6916729 | Salicide formation method | Sunfei Fang, Keith Kwong Hon Wong, Paul D. Agnello, Christian Lavoie, Lawrence A. Clevenger +4 more | 2005-07-12 |
| 6797569 | Method for low topography semiconductor device formation | David Colavito, Phung T. Nguyen | 2004-09-28 |
| 6624486 | Method for low topography semiconductor device formation | David Colavito, Phung T. Nguyen | 2003-09-23 |
| 6544874 | Method for forming junction on insulator (JOI) structure | Jack A. Mandelman, Kevin K. Chan, Bomy Chen, Oleg Gluschenkov, Rajarao Jammy +2 more | 2003-04-08 |
| 6525340 | Semiconductor device with junction isolation | David Colavito | 2003-02-25 |
| 6429091 | Patterned buried insulator | Bomy Chen, Alexander Hirsch, Sundar Iyer, Hsing-Jen Wann, Ying Zhang | 2002-08-06 |
| 6403482 | Self-aligned junction isolation | Chung H. Lam | 2002-06-11 |
| 6391703 | Buried strap for DRAM using junction isolation technique | Chung H. Lam, Rebecca D. Mih | 2002-05-21 |
| 6352903 | Junction isolation | David Colavito | 2002-03-05 |
| 6256755 | Apparatus and method for detecting defective NVRAM cells | Terence B. Hook, Chung H. Lam, Eric Lee, James S. Nakos, Richard Q. Williams +1 more | 2001-07-03 |
| 6071767 | High performance/high density BICMOS process | Michael D. Monkowski, Seiki Ogura, Joseph F. Shepard, Jr. | 2000-06-06 |
| 5892257 | Packing density for flash memories | Joyce Elizabeth Acocella, Carol Galli, Louis L. Hsu, Seiki Ogura, Joseph F. Shepard, Jr. | 1999-04-06 |
| 5681770 | Process for making and programming a flash memory array | Seiki Ogura, Robert C. Wong | 1997-10-28 |