Issued Patents All Time
Showing 101–113 of 113 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6989321 | Low-pressure deposition of metal layers from metal-carbonyl precursors | Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Masahito Sugiura +3 more | 2006-01-24 |
| 6975032 | Copper recess process with application to selective capping and electroless plating | Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin +11 more | 2005-12-13 |
| 6974531 | Method for electroplating on resistive substrates | Panayotis Andricacos, Hariklia Deligianni, Wilma Jean Horkans, Keith Kwietniak, Michael Lane +4 more | 2005-12-13 |
| 6949461 | Method for depositing a metal layer on a semiconductor interconnect structure | Andrew H. Simon | 2005-09-27 |
| 6924223 | Method of forming a metal layer using an intermittent precursor gas flow process | Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Mitsuhiro Tachibana +6 more | 2005-08-02 |
| 6909772 | Method and apparatus for thin film thickness mapping | Krzysztof Kozaczek, David S. Kurtz, Paul R. Moran, Roger Isaac Martin, Patrick W. DeHaven +1 more | 2005-06-21 |
| 6792075 | Method and apparatus for thin film thickness mapping | Krzysztof Kozaczek, David S. Kurtz, Paul R. Moran, Roger Isaac Martin, Patrick W. DeHaven +1 more | 2004-09-14 |
| 6660330 | Method for depositing metal films onto substrate surfaces utilizing a chamfered ring support | Peter S. Locke, Fenton R. McFeely, Andrew H. Simon, John J. Yurkas | 2003-12-09 |
| 6395164 | Copper seed layer repair technique using electroless touch-up | Panayotis Andricacos, James E. Fluegel, John G. Gaudiello, Ronald D. Goldblatt, Milan Paunovic | 2002-05-28 |
| 6380075 | Method for forming an open-bottom liner for a conductor in an electronic structure and device formed | Cyril Cabral, Jr., Chao-Kun Hu, Fenton R. McFeely, Stephen M. Rossnagel, Andrew H. Simon | 2002-04-30 |
| 6358832 | Method of forming barrier layers for damascene interconnects | Daniel C. Edelstein, Timothy J. Dalton, John G. Gaudiello, Mahadevaiyer Krishnan, Maurice McGlashan-Powell +2 more | 2002-03-19 |
| 6153935 | Dual etch stop/diffusion barrier for damascene interconnects | Daniel C. Edelstein, Timothy J. Dalton, John G. Gaudiello, Mahadevaiyer Krishnan, Maurice McGlashan-Powell +2 more | 2000-11-28 |
| 6090722 | Process for fabricating a semiconductor structure having a self-aligned spacer | Michael D. Armacost, Tina Wagner, Richard S. Wise | 2000-07-18 |