Issued Patents All Time
Showing 101–125 of 340 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11374100 | Source or drain structures with contact etch stop layer | Cory Bomberger, Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Tahir Ghani | 2022-06-28 |
| 11355621 | Non-planar semiconductor device including a replacement channel structure | Gilbert Dewey, Willy Rachmady, Sean T. Ma, Nicholas G. Minutillo, Tahir Ghani +2 more | 2022-06-07 |
| 11335600 | Integration method for finfet with tightly controlled multiple fin heights | Seiyon Kim, Jack T. Kavalieros, Glenn A. Glass, Karthik Jambunathan | 2022-05-17 |
| 11328988 | Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication | Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal +1 more | 2022-05-10 |
| 11302777 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more | 2022-04-12 |
| 11296079 | PMOS and NMOS contacts in common trench | Glenn A. Glass | 2022-04-05 |
| 11276755 | Field effect transistors with gate electrode self-aligned to semiconductor fin | Sean T. Ma, Matthew V. Metz, Willy Rachmady, Gilbert Dewey, Chandra S. Mohapatra +2 more | 2022-03-15 |
| 11276694 | Transistor structure with indium phosphide channel | Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Nicholas G. Minutillo, Cheng-Ying Huang +2 more | 2022-03-15 |
| 11264501 | Device, method and system for promoting channel stress in a NMOS transistor | Rishabh Mehandru, Karthik Jambunathan, Cory Bomberger | 2022-03-01 |
| 11257904 | Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) | Cheng-Ying Huang, Tahir Ghani, Jack T. Kavalieros, Harold W. Kennel, Gilbert Dewey +4 more | 2022-02-22 |
| 11251302 | Epitaxial oxide plug for strained transistors | Karthik Jambunathan, Biswajeet Guha, Anupama Bowonder, Tahir Ghani | 2022-02-15 |
| 11251281 | Contact resistance reduction employing germanium overlayer pre-contact metalization | Glenn A. Glass, Tahir Ghani | 2022-02-15 |
| 11244943 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady +5 more | 2022-02-08 |
| 11233148 | Reducing band-to-band tunneling in semiconductor devices | Benjamin Chu-Kung, Jack T. Kavalieros, Seung Hoon Sung, Siddharth Chouksey, Harold W. Kennel +4 more | 2022-01-25 |
| 11232948 | Layered substrate for microelectronic devices | Glenn A. Glass | 2022-01-25 |
| 11222977 | Source/drain diffusion barrier for germanium NMOS transistors | Glenn A. Glass, Karthik Jambunathan, Cory Bomberger, Tahir Ghani, Jack T. Kavalieros +3 more | 2022-01-11 |
| 11205707 | Optimizing gate profile for performance and gate fill | Nadia M. Rahhal-Orabi, Tahir Ghani, Willy Rachmady, Matthew V. Metz, Jack T. Kavalieros +2 more | 2021-12-21 |
| 11195919 | Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Kelin J. Kuhn +1 more | 2021-12-07 |
| 11189730 | Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium nMOS transistors | Glenn A. Glass, Karthik Jambunathan, Cory Bomberger, Tahir Ghani, Jack T. Kavalieros +3 more | 2021-11-30 |
| 11177255 | Transistor structures having multiple threshold voltage channel materials | Sean T. Ma, Willy Rachmady, Gilbert Dewey, Matthew V. Metz, Harold W. Kennel +3 more | 2021-11-16 |
| 11171057 | Semiconductor fin design to mitigate fin collapse | Glenn A. Glass, Chytra Pawashe, Daniel Pantuso, Tahir Ghani | 2021-11-09 |
| 11171058 | Self-aligned 3-D epitaxial structures for MOS device fabrication | Glenn A. Glass, Daniel B. Aubertine, Gaurav Thareja, Tahir Ghani | 2021-11-09 |
| 11171207 | Transistor with isolation below source and drain | Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma +3 more | 2021-11-09 |
| 11164747 | Group III-V semiconductor devices having asymmetric source and drain structures | Sean T. Ma, Gilbert Dewey, Willy Rachmady, Harold W. Kennel, Cheng-Ying Huang +3 more | 2021-11-02 |
| 11164785 | Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material | Ashish Agrawal, Gilbert Dewey, Cheng-Ying Huang, Willy Rachmady, Ryan Keech +1 more | 2021-11-02 |