Issued Patents All Time
Showing 176–200 of 251 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6777737 | Vertical DRAM punchthrough stop self-aligned to storage trench | Jack A. Mandelman, Dureseti Chidambarrao | 2004-08-17 |
| 6767781 | Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask | Larry Nesbit, Jonathan E. Faltermeier, Wolfgang Bergner | 2004-07-27 |
| 6759291 | Self-aligned near surface strap for high density trench DRAMS | Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier, Gary B. Bronner | 2004-07-06 |
| 6759702 | Memory cell with vertical transistor and trench capacitor with reduced burried strap | Carl Radens, Jack A. Mandelman | 2004-07-06 |
| 6750097 | Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby | Jack A. Mandelman | 2004-06-15 |
| 6727540 | Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact | Babar A. Khan, Carl Radens | 2004-04-27 |
| 6727539 | Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ulrike Gruening, Jack A. Mandelman, Larry Nesbit, Carl Radens | 2004-04-27 |
| 6727141 | DRAM having offset vertical transistors and method | Gary B. Bronner, Byeong Y. Kim, Jack A. Mandelman | 2004-04-27 |
| 6724031 | Method for preventing strap-to-strap punch through in vertical DRAMs | Hiroyuki Akatsu, Dureseti Chidambarrao, Jack A. Mandelman, Carl Radens | 2004-04-20 |
| 6703274 | Buried strap with limited outdiffusion and vertical transistor DRAM | Dureseti Chidambarrao, Jack A. Mandelman, Raymond Van Roijen | 2004-03-09 |
| 6693041 | Self-aligned STI for narrow trenches | Jack A. Mandelman, Carl Radens | 2004-02-17 |
| 6686668 | Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask | Larry Nesbit, Johnathan E. Faltermeier, Wolfgang Bergner | 2004-02-03 |
| 6686617 | Semiconductor chip having both compact memory and high performance logic | Paul D. Agnello, Bomy Chen, Scott W. Crowder, Subramanian S. Iyer, Dennis Sinitsky | 2004-02-03 |
| 6670667 | Asymmetric gates for high density DRAM | Wayne F. Ellis, Jack A. Mandelman, Mary E. Weybright | 2003-12-30 |
| 6660581 | Method of forming single bitline contact using line shape masks for vertical transistors in DRAM/e-DRAM devices | Haining Yang | 2003-12-09 |
| 6656817 | Method of filling isolation trenches in a substrate | Laertis Economikos, Byeong Y. Kim | 2003-12-02 |
| 6642566 | Asymmetric inside spacer for vertical transistor | Jack A. Mandelman, Haining Yang | 2003-11-04 |
| 6638815 | Formation of self-aligned vertical connector | Gary B. Bronner | 2003-10-28 |
| 6630379 | Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch | Jack A. Mandelman, Carl Radens, Ulrike Gruening | 2003-10-07 |
| 6596592 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Russell J. Houghton, Jack A. Mandelman, William R. Tonti | 2003-07-22 |
| 6590259 | Semiconductor device of an embedded DRAM on SOI substrate | James W. Adkisson, Jeffrey P. Gambino, Jack A. Mandelman | 2003-07-08 |
| 6579759 | Formation of self-aligned buried strap connector | Michael P. Chudzik, Jochen Beintner, Rajarao Jammy | 2003-06-17 |
| 6573561 | Vertical MOSFET with asymmetrically graded channel doping | Dureseti Chidambarrao, Jack A. Mandelman, Kevin McStay | 2003-06-03 |
| 6573137 | Single sided buried strap | Jack A. Mandelman, Wolfgang Bergner, Gary B. Bronner, Ulrike Gruening, Stephan Kudelka +5 more | 2003-06-03 |
| 6570208 | 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI | Jack A. Mandelman, Carl Radens, Gary B. Bronner | 2003-05-27 |