Issued Patents All Time
Showing 226–250 of 251 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6420749 | Trench field shield in trench isolation | Jeffrey P. Gambino, Edward W. Kiewra, Jack A. Mandelman, Carl Radens, William R. Tonti | 2002-07-16 |
| 6414347 | Vertical MOSFET | Heon Lee, Jack A. Mandelman, Carl Radens, Jai-Hoon Sim | 2002-07-02 |
| 6406962 | Vertical trench-formed dual-gate FET device structure and method for creation | Paul D. Agnello, Arne Ballantine, Erin C. Jones, Edward J. Nowak, Jed H. Rankin | 2002-06-18 |
| 6403423 | Modified gate processing for optimized definition of array and logic devices on same chip | Mary E. Weybright, Gary B. Bronner, Richard A. Conti, Jeffrey P. Gambino, Peter D. Hoh +1 more | 2002-06-11 |
| 6396121 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Russell J. Houghton, Jack A. Mandelman, William R. Tonti | 2002-05-28 |
| 6376324 | Collar process for reduced deep trench edge bias | Jack A. Mandelman, Carl Radens, Ulrike Gruening, Akira Sudo | 2002-04-23 |
| 6369419 | Self-aligned near surface strap for high density trench DRAMS | Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier, Gary B. Bronner | 2002-04-09 |
| 6350653 | Embedded DRAM on silicon-on-insulator substrate | James W. Adkisson, Jeffrey P. Gambino, Jack A. Mandelman | 2002-02-26 |
| 6348374 | Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure | Satish D. Athavale, Gary B. Bronner, Ulrike Gruening, Jack A. Mandelman, Carl Radens | 2002-02-19 |
| 6346734 | Modified gate conductor processing for poly length control in high density DRAMS | Mary E. Weybright | 2002-02-12 |
| 6339241 | Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch | Jack A. Mandelman, Carl Radens, Ulrike Gruening | 2002-01-15 |
| 6333220 | Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact | Jack A. Mandelman | 2001-12-25 |
| 6326260 | Gate prespacers for high density, high performance DRAMs | James W. Adkisson, Mary E. Weybright, Scott D. Halle, Jeffrey P. Gambino, Heon Lee | 2001-12-04 |
| 6309924 | Method of forming self-limiting polysilicon LOCOS for DRAM cell | Jack A. Mandelman, Irene McStay, Larry Nesbit, Carl Radens, Helmut Tews | 2001-10-30 |
| 6287913 | Double polysilicon process for providing single chip high performance logic and compact embedded memory structure | Paul D. Agnello, Bomy Chen, Scott W. Crowder, Subramanian S. Iyer, Dennis Sinitsky | 2001-09-11 |
| 6284593 | Method for shallow trench isolated, contacted well, vertical MOSFET DRAM | Jack A. Mandelman, Carl Radens | 2001-09-04 |
| 6281084 | Disposable spacers for improved array gapfill in high density DRAMs | Hiroyuki Akatsu, Gill Yong Lee | 2001-08-28 |
| 6281064 | Method for providing dual work function doping and protective insulating cap | Jack A. Mandelman, Gary B. Bronner | 2001-08-28 |
| 6274441 | Method of forming bitline diffusion halo under gate conductor ledge | Jack A. Mandelman, William R. Tonti | 2001-08-14 |
| 6261914 | Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer | Jeffrey P. Gambino, Carl Radens, Jeremy K. Stephens | 2001-07-17 |
| 6261894 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays | Jack A. Mandelman, Carl Radens | 2001-07-17 |
| 6258659 | Embedded vertical DRAM cells and dual workfunction logic gates | Ulrike Gruening, Jack A. Mandelman, Thomas Rupp | 2001-07-10 |
| 6242310 | Method of forming buried-strap with reduced outdiffusion including removing a sacrificial insulator leaving a gap and supporting spacer | Jack A. Mandelman | 2001-06-05 |
| 6214686 | Spatially offset deep trenches for high density DRAMS | Gary B. Bronner | 2001-04-10 |
| 6150212 | Shallow trench isolation method utilizing combination of spacer and fill | Jeffrey P. Gambino, Jack A. Mandelman, Carl Radens, William R. Tonti | 2000-11-21 |