Issued Patents All Time
Showing 201–225 of 251 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6566219 | Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening | Gerhard Kunkel, Shahid Butt, Armin Reith, Munir D. Naeem | 2003-05-20 |
| 6548357 | Modified gate processing for optimized definition of array and logic devices on same chip | Mary E. Weybright, Gary B. Bronner, Richard A. Conti, Jeffrey P. Gambino, Peter D. Hoh +1 more | 2003-04-15 |
| 6541810 | Modified vertical MOSFET and methods of formation thereof | Prakash Dev, Rajeev Malik, Larry Nesbit | 2003-04-01 |
| 6518641 | Deep slit isolation with controlled void | Jack A. Mandelman, Johnathan E. Faltermeier, William R. Tonti | 2003-02-11 |
| 6518118 | Structure and process for buried bitline and single sided buried conductor formation | Satish D. Athavale, Jack A. Mandelman | 2003-02-11 |
| 6509226 | Process for protecting array top oxide | Venkatachalam C. Jaiprakash, Jack A. Mandelman, Rajeev Malik, Mihel Seitz | 2003-01-21 |
| 6503798 | Low resistance strap for high density trench DRAMS | Jeffrey P. Gambino, Herbert L. Ho, Akira Sudo | 2003-01-07 |
| 6504210 | Fully encapsulated damascene gates for Gigabit DRAMs | Jeffrey P. Gambino, Jack A. Mandelman, Viraj Y. Sardesai, Mary E. Weybright | 2003-01-07 |
| 6501117 | Static self-refreshing DRAM structure and operating mode | Carl Radens, Gary B. Bronner, Jack A. Mandelman | 2002-12-31 |
| 6495876 | DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS | Gary B. Bronner, Yoichi Takegawa | 2002-12-17 |
| 6492211 | Method for novel SOI DRAM BICMOS NPN | Russell J. Houghton, Jack A. Mandelman, W. David Pricer, William R. Tonti | 2002-12-10 |
| 6458646 | Asymmetric gates for high density DRAM | Wayne F. Ellis, Jack A. Mandelman, Mary E. Weybright | 2002-10-01 |
| 6455886 | Structure and process for compact cell area in a stacked capacitor cell array | Jack A. Mandelman, Carl Radens | 2002-09-24 |
| 6448590 | Multiple threshold voltage FET using multiple work-function gate materials | James W. Adkisson, Arne Ballantine, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum Philip Wong | 2002-09-10 |
| 6448131 | Method for increasing the capacitance of a trench capacitor | Cyril Cabral, Jr., Kevin K. Chan, Guy M. Cohen, Christian Lavoie, Fenton R. McFeely | 2002-09-10 |
| 6444548 | Bitline diffusion with halo for improved array threshold voltage control | Yujun Li, Jack A. Mandelman | 2002-09-03 |
| 6441422 | Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well | Jack A. Mandelman, Carl Radens, Jai-Hoon Sim | 2002-08-27 |
| 6440793 | Vertical MOSFET | Heon Lee, Jack A. Mandelman, Carl Radens, Jai-Hoon Sim | 2002-08-27 |
| 6440872 | Method for hybrid DRAM cell utilizing confined strap isolation | Jack A. Mandelman, Carl Radens, Stephan Kudelka | 2002-08-27 |
| 6432787 | Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact | Jack A. Mandelman | 2002-08-13 |
| 6429101 | Method of forming thermally stable polycrystal to single crystal electrical contact structure | Ricky S. Amos, Arne Ballantine, Gregory Bazan, Bomy Chen, Douglas D. Coolbaugh +6 more | 2002-08-06 |
| 6429068 | Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ulrike Gruening, Jack A. Mandelman, Larry Nesbit, Carl Radens | 2002-08-06 |
| 6426247 | Low bitline capacitance structure and method of making same | Jeffrey P. Gambino, Jack A. Mandelman, Rajesh Rengarajan | 2002-07-30 |
| 6426526 | Single sided buried strap | Jack A. Mandelman, Gary B. Bronner, Carl Radens | 2002-07-30 |
| 6420750 | Structure and method for buried-strap with reduced outdiffusion | Jack A. Mandelman | 2002-07-16 |