Issued Patents All Time
Showing 151–175 of 251 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7091553 | Top oxide nitride liner integration scheme for vertical DRAM | Klaus Hummler | 2006-08-15 |
| 7060546 | Ultra-thin SOI MOSFET method and structure | Louis C. Hsu, Carl Radens | 2006-06-13 |
| 7041553 | Process for forming a buried plate | Cheng Kangguo | 2006-05-09 |
| 7037794 | Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain | Jochen Beintner, Gary B. Bronner, Byeong Y. Kim | 2006-05-02 |
| 7030012 | Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM | Oleg Gluschenkov, Oh-Jung Kwon, Rajeev Malik | 2006-04-18 |
| 7022622 | Method and structure to improve properties of tunable antireflective coatings | Kangguo Cheng | 2006-04-04 |
| 7009237 | Out of the box vertical transistor for eDRAM on SOI | James W. Adkisson, Gary B. Bronner, Dureseti Chidambarrao, Carl Radens | 2006-03-07 |
| 6972220 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Russell J. Houghton, Jack A. Mandelman, William R. Tonti | 2005-12-06 |
| 6972266 | Top oxide nitride liner integration scheme for vertical DRAM | Klaus Hummler | 2005-12-06 |
| 6969648 | Method for forming buried plate of trench capacitor | Kangguo Cheng | 2005-11-29 |
| 6943409 | Trench optical device | Kangguo Cheng, Carl Radens | 2005-09-13 |
| 6936511 | Inverted buried strap structure and method for vertical transistor DRAM | Thomas W. Dyer | 2005-08-30 |
| 6933192 | Method for fabricating a trench having a buried dielectric collar | Ravikumar Ramachandran, Chun-Yung Sung | 2005-08-23 |
| 6913968 | Method and structure for vertical DRAM devices with self-aligned upper trench shaping | Kangguo Cheng, C.Y. Sung | 2005-07-05 |
| 6908806 | Gate metal recess for oxidation protection and parasitic capacitance reduction | Haining Yang, Oleg Gluschenkov, Rajeev Malik, Hongwen Yan, Ravikumar Ramachandran | 2005-06-21 |
| 6909137 | Method of creating deep trench capacitor using a P+ metal electrode | Jack A. Mandelman, Dae-Gyu Park | 2005-06-21 |
| 6833305 | Vertical DRAM punchthrough stop self-aligned to storage trench | Jack A. Mandelman, Dureseti Chidambarrao | 2004-12-21 |
| 6831006 | Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner | Jack A. Mandelman, Haining Yang | 2004-12-14 |
| 6830968 | Simplified top oxide late process | Deok-kee Kim | 2004-12-14 |
| 6818528 | Method for multi-depth trench isolation | Jack A. Mandelman | 2004-11-16 |
| 6808981 | Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI | Jack A. Mandelman, Carl Radens, Gary B. Bronner | 2004-10-26 |
| 6797553 | Method for making multiple threshold voltage FET using multiple work-function gate materials | James W. Adkisson, Arne Ballantine, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum Philip Wong | 2004-09-28 |
| 6790722 | Logic SOI structure, process and application for vertical bipolar transistor | Russell J. Houghton, Jack A. Mandelman, Wilbur D. Pricer, William R. Tonti | 2004-09-14 |
| 6787838 | Trench capacitor DRAM cell using buried oxide as array top oxide | Dureseti Chidambarrao, Deok-kee Kim | 2004-09-07 |
| 6777733 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays | Jack A. Mandelman, Carl Radens | 2004-08-17 |