Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9665372 | Parallel slice processor with dynamic instruction stream mapping | Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti, Brian W. Thompto +1 more | 2017-05-30 |
| 9594561 | Instruction stream tracing of multi-threaded processors | Lisa C. Heller, Michael T. Huffer, Eric M. Schwarz | 2017-03-14 |
| 9146772 | Reducing power grid noise in a processor while minimizing performance loss | Michael Stephen Floyd, Thomas Strach, Huajun Wen, Tingdong Zhou | 2015-09-29 |
| 9141421 | Reducing power grid noise in a processor while minimizing performance loss | Michael Stephen Floyd, Thomas Strach, Huajun Wen, Tingdong Zhou | 2015-09-22 |
| 9104399 | Dual issuing of complex instruction set instructions | Fadi Y. Busaba, Brian W. Curran, Christian Jacobi, David A. Schroter, Eric M. Schwarz | 2015-08-11 |
| 8683180 | Intermediate register mapper | Brian D. Barrick, Michael Billeci | 2014-03-25 |
| 8464030 | Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits | Fadi Y. Busaba, Brian W. Curran, Bruce C. Giamei, David S. Hutton | 2013-06-11 |
| 7904697 | Load register instruction short circuiting method | Brian D. Barrick, Brian W. Curran | 2011-03-08 |
| 7890738 | Method and logical apparatus for managing processing system resource use for speculative execution | David S. Levitan, Francis Patrick O'Connell, Wolfram Sauer | 2011-02-15 |
| 7769984 | Dual-issuance of microprocessor instructions using dual dependency matrices | Gregory W. Alexander, Brian D. Barrick, John W. Ward, III | 2010-08-03 |
| 7549095 | Error detection enhancement in a microprocessor through the use of a second dependency matrix | Gregory W. Alexander, Brian W. Thompto, John W. Ward, III | 2009-06-16 |
| 7392366 | Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches | Pradip Bose, Alper Buyuktosunoglu, Richard J. Eickemeyer, Philip G. Emma, John B. Griswell, Jr. +4 more | 2008-06-24 |
| 7254693 | Selectively prohibiting speculative execution of conditional branch type based on instruction bit | Francis Patrick O'Connell | 2007-08-07 |
| 7194645 | Method and apparatus for autonomic policy-based thermal management in a data processing system | Andreas Bieswanger, James Stephen Fields, Jr., Michael Stephen Floyd, Bradley McCredie, Naresh Nayar | 2007-03-20 |
| 6848044 | Circuits and methods for recovering link stack data upon branch instruction mis-speculation | James Allan Kahle, Balaram Sinharoy, William J. Starke | 2005-01-25 |
| 6442675 | Compressed string and multiple generation engine | John Edward Derrick, Hung Q. Le | 2002-08-27 |
| 6430678 | Scoreboard mechanism for serialized string operations utilizing the XER | James Allan Kahle, Hung Q. Le, John Edward Derrick, Robert William Hay | 2002-08-06 |
| 6385719 | Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor | John Edward Derrick, Brian R. Konigsburg, David S. Levitan | 2002-05-07 |
| 6345356 | Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs | John Edward Derrick, Hung Q. Le, Robert G. McDonald | 2002-02-05 |
| 6336182 | System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch | John Edward Derrick, Paul J. Jordan, Robert William Hay | 2002-01-01 |
| 6321380 | Method and apparatus for modifying instruction operations in a processor | John Edward Derrick, Kevin F. Reick | 2001-11-20 |
| 6286094 | Method and system for optimizing the fetching of dispatch groups in a superscalar processor | John Edward Derrick, Hung Q. Le, Brian R. Konigsburg | 2001-09-04 |
| 6098168 | System for completing instruction out-of-order which performs target address comparisons prior to dispatch | Michael Putrino | 2000-08-01 |
| 5897654 | Method and system for efficiently fetching from cache during a cache fill operation | Belliappa Kuttanna, Soummya Mallick, Rajesh Patel | 1999-04-27 |
| 5809323 | Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor | Robert T. Golla, Soummya Mallick, Sung Ho Park, Rajesh B. Patel, Michael Putrino | 1998-09-15 |