Issued Patents All Time
Showing 126–150 of 213 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9601513 | Subsurface wires of integrated chip and methods of forming | Terence B. Hook, Andreas Scholze, Roger QUON, Andrew H. Simon | 2017-03-21 |
| 9570573 | Self-aligned gate tie-down contacts with selective etch stop liner | Su Chen Fan, Ruilong Xie | 2017-02-14 |
| 9424386 | Generating place and route abstracts | Albert M. Chu | 2016-08-23 |
| 9418935 | Integrated circuit line ends formed using additive processing | Dongbing Shao, Lei Zhuang, Lawrence A. Clevenger | 2016-08-16 |
| 9397049 | Gate tie-down enablement with inner spacer | Su Chen Fan, Andre P. Labonte, Sanjay C. Mehta | 2016-07-19 |
| 9385078 | Self aligned via in integrated circuit | Yannick Feurprier, Joe Lee, Yann Mignot, Terry A. Spooner, Douglas M. Trickett +1 more | 2016-07-05 |
| 9373582 | Self aligned via in integrated circuit | Yannick Feurprier, Joe Lee, Yann Mignot, Terry A. Spooner, Douglas M. Trickett +1 more | 2016-06-21 |
| 9335626 | Mask design and decomposition for sidewall image transfer | Neal V. Lafferty | 2016-05-10 |
| 9245076 | Orthogonal circuit element routing | Vassilios Gerousis, Stefanus Mantik, Gustavo E. Tellez, Shuo Zhang | 2016-01-26 |
| 9158885 | Reducing color conflicts in triple patterning lithography | Michael S. Gray, Matthew T. Guzowski, Alexander Ivrii, Kevin W. McCullen, Gustavo E. Tellez +1 more | 2015-10-13 |
| 8647893 | Method for post decomposition density balancing in integrated circuit layouts, related system and program product | Kanak B. Agarwal, Shayak Banerjee | 2014-02-11 |
| 8627245 | Density balancing in multiple patterning lithography using integrated circuit layout fill | Shayak Banerjee, Ian P. Stobert | 2014-01-07 |
| 8584060 | Block mask decomposition for mitigating corner rounding | William Brearley, Geng Han | 2013-11-12 |
| 8516403 | Multiple patterning layout decomposition for ease of conflict removal | Rani S. Abou Ghaida, Kanak B. Agarwal, Sani R. Nassif | 2013-08-20 |
| 8473885 | Physical design system and method | John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin +6 more | 2013-06-25 |
| 8434033 | Mask assignment for multiple patterning lithography | Rani S. Abou Ghaida, Kanak B. Agarwal, Sani R. Nassif | 2013-04-30 |
| 8347246 | Placement and optimization of process dummy cells | Xu Ouyang, Geng Han | 2013-01-01 |
| 8347240 | Split-layer design for double patterning lithography | Kanak B. Agarwal, Sani R. Nassif | 2013-01-01 |
| 8302068 | Leakage aware design post-processing | James A. Culp | 2012-10-30 |
| 8225255 | Placement and optimization of process dummy cells | Xu Ouyang, Geng Han | 2012-07-17 |
| 8219943 | Physical design system and method | John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin +6 more | 2012-07-10 |
| 8214770 | Multilayer OPC for design aware manufacturing | Maharaj Mukherjee, James A. Culp, Scott M. Mansfield | 2012-07-03 |
| 8181126 | Differential alternating phase shift mask optimization | Zachary Baum | 2012-05-15 |
| 8141027 | Automated sensitivity definition and calibration for design for manufacturing tools | James A. Culp, Jason D. Hibbeler, Tina Wagner | 2012-03-20 |
| 8103983 | Electrically-driven optical proximity correction to compensate for non-optical effects | Kanak B. Agarwal, Shayak Banerjee, Praveen Elakkumanan | 2012-01-24 |