Issued Patents All Time
Showing 826–850 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10559491 | Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap | Zuoguang Liu, Sebastian Naczas, Heng Wu, Peng Xu | 2020-02-11 |
| 10553716 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Fee Li Lie, Shogo Mochizuki, Junli Wang | 2020-02-04 |
| 10553705 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Ruilong Xie, Steven R. Bentley, Nicolas Loubet, Pietro Montanini | 2020-02-04 |
| 10553691 | Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts | Peng Xu | 2020-02-04 |
| 10553682 | Vertical transistors with multiple gate lengths | Zhenxing Bi, Peng Xu, Zheng Xu | 2020-02-04 |
| 10553581 | Air gap spacer for metal gates | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2020-02-04 |
| 10553495 | Nanosheet transistors with different gate dielectrics and workfunction metals | Choonghyun Lee, Juntao Li, Peng Xu | 2020-02-04 |
| 10553493 | Fabrication of a vertical transistor with self-aligned bottom source/drain | Xin Miao, Wenyu Xu, Chen Zhang | 2020-02-04 |
| 10553445 | Stacked nanowires | Zhenxing Bi, Juntao Li, Xin Miao | 2020-02-04 |
| 10553354 | Method of manufacturing inductor with ferromagnetic cores | Juntao Li, Geng Wang, Qintao Zhang | 2020-02-04 |
| 10546955 | Dielectric isolated fin with improved fin profile | Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim | 2020-01-28 |
| 10546945 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Ruilong Xie, Steven R. Bentley, Nicolas Loubet, Pietro Montanini | 2020-01-28 |
| 10546942 | Nanosheet transistor with optimized junction and cladding defectivity control | Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-01-28 |
| 10546940 | On-chip integrated temperature protection device based on gel electrolyte | Qing Cao, Zhengwen Li, Fei Liu | 2020-01-28 |
| 10546857 | Vertical transistor transmission gate with adjacent NFET and PFET | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2020-01-28 |
| 10546788 | Dual channel FinFETs having uniform fin heights | Zhenxing Bi, Peng Xu, Jie Yang | 2020-01-28 |
| 10544042 | Nanoparticle structure and process for manufacture | Qing Cao, Juntao Li | 2020-01-28 |
| 10541335 | Stress induction in 3D device channel using elastic relaxation of high stress material | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2020-01-21 |
| 10541330 | Forming stacked nanowire semiconductor device | Xin Miao, Peng Xu, Chen Zhang | 2020-01-21 |
| 10541312 | Air-gap top spacer and self-aligned metal gate for vertical fets | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-01-21 |
| 10541308 | Gate cut device fabrication with extended height gates | Andrew M. Greene, John R. Sporre, Peng Xu | 2020-01-21 |
| 10541253 | FinFETs with various fin height | Terence B. Hook, Xin Miao, Balasubramanian Pranatharthiharan | 2020-01-21 |
| 10541203 | Nickel-silicon fuse for FinFET structures | Keith E. Fogel, Pouya Hashemi, Alexander Reznicek | 2020-01-21 |
| 10541177 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2020-01-21 |
| 10541176 | Vertical silicon/silicon-germanium transistors with multiple threshold voltages | Zhenxing Bi, Juntao Li, Peng Xu | 2020-01-21 |