Issued Patents All Time
Showing 851–875 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10541172 | Semiconductor device with reduced contact resistance | Sean Teehan, Alex Varghese | 2020-01-21 |
| 10541128 | Method for making VFET devices with ILD protection | Zhenxing Bi, Juntao Li, Peng Xu | 2020-01-21 |
| 10539528 | Stacked nanofluidics structure | — | 2020-01-21 |
| 10535755 | Closely packed vertical transistors with reduced contact resistance | Zhenxing Bi, Juntao Li, Peng Xu | 2020-01-14 |
| 10535754 | Method and structure for forming a vertical field-effect transistor | Peng Xu, Choonghyun Lee, Juntao Li | 2020-01-14 |
| 10535733 | Method of forming a nanosheet transistor | Choonghyun Lee, Juntao Li, Peng Xu | 2020-01-14 |
| 10535652 | Fabrication of vertical fin field effect transistors having top air spacers and a self-aligned top junction | Xin Miao, Wenyu Xu, Chen Zhang | 2020-01-14 |
| 10535567 | Methods and structures for forming uniform fins when using hardmask patterns | Peng Xu, Yann Mignot, Choonghyun Lee | 2020-01-14 |
| 10529713 | Fin field effect transistor devices with modified spacer and gate dielectric thicknesses | Xin Miao, Wenyu Xu, Chen Zhang | 2020-01-07 |
| 10530364 | Multiple programmable hardware-based on-chip password | — | 2020-01-07 |
| 10529851 | Forming bottom source and drain extension on vertical transport FET (VTFET) | Shogo Mochizuki, Juntao Li, Choonghyun Lee | 2020-01-07 |
| 10529829 | Silicon germanium alloy fins with reduced defects | Hong He, Juntao Li | 2020-01-07 |
| 10529826 | Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices | Julien Frougier, Ruilong Xie, Chanro Park | 2020-01-07 |
| 10529823 | Method of manufacturing a semiconductor device having a metal gate with different lateral widths between spacers | Xin Miao, Chen Zhang, Wenyu Xu | 2020-01-07 |
| 10522658 | Vertical field effect transistor having improved uniformity | Juntao Li, Ruilong Xie, Chanro Park | 2019-12-31 |
| 10522678 | Vertical transistor pass gate device | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-12-31 |
| 10522661 | Integrated strained stacked nanosheet FET | Ramachandra Divakaruni, Juntao Li, Xin Miao | 2019-12-31 |
| 10522636 | Fin field-effect transistor for input/output device integrated with nanosheet field-effect transistor | Chun Wing Yeung, Chen Zhang, Peng Xu, Huiming Bu | 2019-12-31 |
| 10522649 | Inverse T-shaped contact structures having air gap spacers | Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu | 2019-12-31 |
| 10522594 | Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element | Peng Xu, Juntao Li, Choonghyun Lee | 2019-12-31 |
| 10516028 | Transistor with asymmetric spacers | Zhenxing Bi, Heng Wu, Peng Xu | 2019-12-24 |
| 10516064 | Multiple width nanosheet devices | Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang | 2019-12-24 |
| 10510885 | Transistor with asymmetric source/drain overlap | Peng Xu, Heng Wu, Zhenxing Bi | 2019-12-17 |
| 10510892 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu | 2019-12-17 |
| 10504793 | Hybrid-channel nano-sheet FETs | Zhenxing Bi, Peng Xu, Wenyu Xu | 2019-12-10 |