Issued Patents All Time
Showing 801–825 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10573724 | Contact over active gate employing a stacked spacer | — | 2020-02-25 |
| 10573566 | Fabrication of fin field effect transistor complementary metal-oxide-semiconductor devices with uniform hybrid channels | Zhenxing Bi, Peng Xu, Jie Yang | 2020-02-25 |
| 10573561 | Formation of stacked nanosheet semiconductor devices | Juntao Li, Heng Wu, Peng Xu | 2020-02-25 |
| 10573482 | Piezoelectric vacuum transistor | Qing Cao, Zhengwen Li, Fei Liu | 2020-02-25 |
| 10566445 | Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates | Zhenxing Bi, Nicolas Loubet, Xin Miao, Wenyu Xu, Chen Zhang | 2020-02-18 |
| 10566444 | Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance | Chen Zhang, Xin Miao, Wenyu Xu | 2020-02-18 |
| 10566443 | Nanosheet transitor with optimized junction and cladding defectivity control | Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-02-18 |
| 10566442 | Vertical field effect transistor with reduced parasitic capacitance | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-02-18 |
| 10566438 | Nanosheet transistor with dual inner airgap spacers | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2020-02-18 |
| 10566436 | Steep-switch field effect transistor with integrated bi-stable resistive system | Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh | 2020-02-18 |
| 10566430 | Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts | Peng Xu | 2020-02-18 |
| 10566349 | FinFET with stacked faceted S/D epitaxy for improved contact resistance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2020-02-18 |
| 10566251 | Techniques for forming vertical transport FET | Choonghyun Lee, Juntao Li | 2020-02-18 |
| 10566246 | Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices | Heng Wu, Junli Wang, Zuoguang Liu | 2020-02-18 |
| 10566240 | Wimpy device by selective laser annealing | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2020-02-18 |
| 10564125 | Self-aligned nanotips with tapered vertical sidewalls | Juntao Li, Peng Xu, Heng Wu | 2020-02-18 |
| 10559690 | Embedded source/drain structure for tall FinFET and method of formation | Veeraraghavan S. Basker, Ali Khakifirooz, Henry K. Utomo, Reinaldo Vega | 2020-02-11 |
| 10559685 | Vertical field effect transistor with reduced external resistance | Juntao Li, Choonghyun Lee, Peng Xu | 2020-02-11 |
| 10559675 | Stacked silicon nanotubes | Juntao Li, Choonghyun Lee, Peng Xu | 2020-02-11 |
| 10559662 | Hybrid aspect ratio trapping | Ramachandra Divakaruni, Hong He, Juntao Li | 2020-02-11 |
| 10559625 | RRAM cells in crossbar array architecture | Dexin Kong, Takashi Ando, Juntao Li | 2020-02-11 |
| 10559566 | Reduction of multi-threshold voltage patterning damage in nanosheet device structure | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2020-02-11 |
| 10559542 | Chip security fingerprint | Shawn P. Fetterolf, Chi-Chun Liu | 2020-02-11 |
| 10559504 | High mobility semiconductor fins on insulator | Xin Miao, Wenyu Xu, Chen Zhang | 2020-02-11 |
| 10559502 | Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain | Xin Miao, Wenyu Xu, Chen Zhang | 2020-02-11 |