Issued Patents All Time
Showing 776–800 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10593672 | Method and structure of forming strained channels for CMOS device fabrication | Juntao Li, John G. Gaudiello | 2020-03-17 |
| 10593663 | Distributed decoupling capacitor | Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi | 2020-03-17 |
| 10593622 | Electrical fuse and/or resistors structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2020-03-17 |
| 10593598 | Vertical FET with various gate lengths by an oxidation process | Xin Miao, Chen Zhang | 2020-03-17 |
| 10592698 | Analog-based multiple-bit chip security | Xin Miao, Wenyu Xu, Chen Zhang | 2020-03-17 |
| 10586867 | Strained FinFET source drain isloation | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-03-10 |
| 10586858 | Fabrication of vertical field effect transistor structure with strained channels | Juntao Li | 2020-03-10 |
| 10586857 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-03-10 |
| 10586843 | Tunable on-chip nanosheet resistor | Zhenxing Bi, Wei Wang, Zheng Xu | 2020-03-10 |
| 10586800 | Anti-fuse with reduced programming voltage | Juntao Li, Chengwen Pei, Geng Wang | 2020-03-10 |
| 10586799 | Multiple-bit electrical fuses | Ramachandra Divakaruni | 2020-03-10 |
| 10586741 | Gate height and spacer uniformity | Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John H. Zhang | 2020-03-10 |
| 10586739 | Self-aligned punch through stopper liner for bulk FinFET | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-03-10 |
| 10586737 | Method and structure for forming vertical transistors with shared gates and separate gates | Zhenxing Bi, Juntao Li, Peng Xu | 2020-03-10 |
| 10580880 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-03-03 |
| 10580855 | High thermal budget compatible punch through stop integration using doped glass | Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh | 2020-03-03 |
| 10580854 | High thermal budget compatible punch through stop integration using doped glass | Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh | 2020-03-03 |
| 10580770 | Vertical transistors with different gate lengths | Xin Miao, Chen Zhang, Juntao Li | 2020-03-03 |
| 10580743 | Prevention of reverse engineering of security chips | Qing Cao, Zhengwen Li, Fei Liu | 2020-03-03 |
| 10580709 | Flipped vertical field-effect-transistor | Xin Miao, Wenyu Xu, Chen Zhang | 2020-03-03 |
| 10580704 | Semiconductor devices with sidewall spacers of equal thickness | Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2020-03-03 |
| 10580692 | Integration of air spacer with self-aligned contact in transistor | Chanro Park, Ruilong Xie, Julien Frougier | 2020-03-03 |
| 10573755 | Nanosheet FET with box isolation on substrate | Julien Frougier, Nicolas Loubet, Ruilong Xie | 2020-02-25 |
| 10573745 | Super long channel device within VFET architecture | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2020-02-25 |
| 10573726 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2020-02-25 |