Issued Patents All Time
Showing 901–925 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10453920 | Techniques for forming finFET transistors with same fin pitch and different source/drain epitaxy configurations | Peng Xu | 2019-10-22 |
| 10453934 | Vertical transport FET devices having air gap top spacer | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-10-22 |
| 10453939 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-10-22 |
| 10446650 | FinFET with a silicon germanium alloy channel and method of fabrication thereof | Bruce B. Doris, Hong He, Ali Khakifirooz | 2019-10-15 |
| 10446664 | Inner spacer formation and contact resistance reduction in nanosheet transistors | Choonghyun Lee, Juntao Li, Peng Xu | 2019-10-15 |
| 10446686 | Asymmetric dual gate fully depleted transistor | Terry Hook, Yi Song, Chen Zhang, Xin Miao, Peng Xu | 2019-10-15 |
| 10446452 | Method and structure for enabling controlled spacer RIE | Ryan O. Jung, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre +1 more | 2019-10-15 |
| 10446647 | Approach to minimization of strain loss in strained fin field effect transistors | Zhenxing Bi, Juntao Li, Peng Xu | 2019-10-15 |
| 10438850 | Semiconductor device with local connection | Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang | 2019-10-08 |
| 10438855 | Dual channel FinFETs having uniform fin heights | Zhenxing Bi, Peng Xu, Jie Yang | 2019-10-08 |
| 10438972 | Sub-fin removal for SOI like isolation with uniform active fin height | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-10-08 |
| 10439031 | Integration of vertical-transport transistors and electrical fuses | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-10-08 |
| 10438949 | Vertical FET with reduced parasitic capacitance | Xin Miao, Philip J. Oldiges, Wenyu Xu, Chen Zhang | 2019-10-08 |
| 10439136 | Nanoparticle with plural functionalities, and method of forming the nanoparticle | Qing Cao, Zhengwen Li, Fei Liu | 2019-10-08 |
| 10439044 | Method and structure of fabricating I-shaped silicon germanium vertical field-effect transistors | Choonghyun Lee, Juntao Li, Peng Xu | 2019-10-08 |
| 10431659 | Fabrication of a vertical fin field effect transistor with a reduced contact resistance | Xin Miao, Wenyu Xu, Chen Zhang | 2019-10-01 |
| 10431660 | Self-limiting fin spike removal | Choonghyun Lee, Juntao Li, Peng Xu | 2019-10-01 |
| 10431495 | Semiconductor device with local connection | Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang | 2019-10-01 |
| 10431557 | Secure semiconductor chip by piezoelectricity | Qing Cao, Fei Liu, Zhengwen Li | 2019-10-01 |
| 10431646 | Electronic devices having spiral conductive structures | Peng Xu, Xuefeng Liu, Chi-Chun Liu, Yongan Xu | 2019-10-01 |
| 10431651 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Cheng Chi, Ruilong Xie, John H. Zhang | 2019-10-01 |
| 10431667 | Vertical field effect transistors with uniform threshold voltage | Xin Miao, Heng Wu, Peng Xu | 2019-10-01 |
| 10424639 | Nanosheet transistor with high-mobility channel | Xin Miao, Wenyu Xu, Chen Zhang | 2019-09-24 |
| 10424651 | Forming nanosheet transistor using sacrificial spacer and inner spacers | Julien Frougier, Nicolas Loubet | 2019-09-24 |
| 10424585 | Decoupling capacitor on strain relaxation buffer layer | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-09-24 |