Issued Patents All Time
Showing 251–275 of 289 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7981772 | Methods of fabricating nanostructures | Brent A. Anderson, Andres Bryant, Edward J. Nowak | 2011-07-19 |
| 7960795 | Partially and fully silicided gate stacks | Leland Chang, Renee T. Mo | 2011-06-14 |
| 7955950 | Semiconductor-on-insulator substrate with a diffusion barrier | Junedong Lee, Dominic J. Schepis, Zhibin Ren | 2011-06-07 |
| 7948307 | Dual dielectric tri-gate field effect transistor | Josephine B. Chang, Leland Chang, Chung-Hsun Lin | 2011-05-24 |
| 7928513 | Protection against charging damage in hybrid orientation transistors | Terence B. Hook, Anda C. Mocuta, Anthony K. Stamper | 2011-04-19 |
| 7893492 | Nanowire mesh device and method of fabricating same | Stephen W. Bedell, Josephine B. Chang, Paul Chang, Michael A. Guillorn | 2011-02-22 |
| 7892945 | Nanowire mesh device and method of fabricating same | Stephen W. Bedell, Josephine B. Chang, Paul Chang, Michael A. Guillorn | 2011-02-22 |
| 7893494 | Method and structure for SOI body contact FET with reduced parasitic capacitance | Leland Chang, Anthony I. Chou, Shreesh Narasimha | 2011-02-22 |
| 7884004 | Maskless process for suspending and thinning nanowires | Sarunya Bangsaruntip, Guy M. Cohen | 2011-02-08 |
| 7879650 | Method of providing protection against charging damage in hybrid orientation transistors | Terence B. Hook, Anda C. Mocuta, Anthony K. Stamper | 2011-02-01 |
| 7859061 | Halo-first ultra-thin SOI FET for superior short channel control | Omer H. Dokumaci, John Michael Hergenrother, Shreesh Narasimha | 2010-12-28 |
| 7855135 | Method to reduce parastic capacitance in a metal high dielectric constant (MHK) transistor | Leland Chang, Isaac Lauer, Renee T. Mo | 2010-12-21 |
| 7843007 | Metal high-k transistor having silicon sidewall for reduced parasitic capacitance | Leland Chang, Isaac Lauer, Renee T. Mo | 2010-11-30 |
| 7826251 | High performance metal gate polygate 8 transistor SRAM cell with reduced variability | Leland Chang | 2010-11-02 |
| 7804140 | Field effect transistor with reduced shallow trench isolation induced leakage current | Leland Chang, Anthony I. Chou, Shreesh Narasimha | 2010-09-28 |
| 7785952 | Partially and fully silicided gate stacks | Leland Chang, Renee T. Mo | 2010-08-31 |
| 7776732 | Metal high-K transistor having silicon sidewall for reduced parasitic capacitance, and process to fabricate same | Leland Chang, Isaac Lauer, Renee T. Mo | 2010-08-17 |
| 7736981 | Metal high dielectric constant transistor with reverse-T gate | Leland Chang, Isaac Lauer | 2010-06-15 |
| 7718496 | Techniques for enabling multiple Vt devices using high-K metal gate stacks | Martin M. Frank, Arvind Kumar, Vijay Narayanan, Vamsi K. Paruchuri | 2010-05-18 |
| 7713807 | High-performance CMOS SOI devices on hybrid crystal-oriented substrates | Bruce B. Doris, Kathryn Guarini, Meikei Ieong, Shreesh Narasimha, Kern Rim +1 more | 2010-05-11 |
| 7687365 | CMOS structure for body ties in ultra-thin SOI (UTSOI) substrates | — | 2010-03-30 |
| 7687863 | Selective incorporation of charge for transistor channels | John Michael Hergenrother, Zhibin Ren, Dinkar Singh | 2010-03-30 |
| 7659583 | Ultrathin SOI CMOS devices employing differential STI liners | Zhibin Ren, Ghavam G. Shahidi, Dinkar Singh, Xinhui Wang | 2010-02-09 |
| 7648868 | Metal-gated MOSFET devices having scaled gate stack thickness | Amlan Majumdar, Renee T. Mo, Zhibin Ren | 2010-01-19 |
| 7605429 | Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement | Kerry Bernstein, Min Yang | 2009-10-20 |