Issued Patents All Time
Showing 76–100 of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9257334 | Double self-aligned via patterning | Yongan Xu, Yunpeng Yin, Ailian Zhao | 2016-02-09 |
| 9219007 | Double self aligned via patterning | Yongan Xu, Yunpeng Yin, Ailian Zhao | 2015-12-22 |
| 9214429 | Trench interconnect having reduced fringe capacitance | John H. Zhang, Lawrence A. Clevenger, Yann Mignot, Carl Radens, Richard S. Wise +2 more | 2015-12-15 |
| 8957519 | Structure and metallization process for advanced technology nodes | Chih-Chao Yang | 2015-02-17 |
| 8859384 | Inductor formation with sidewall image transfer | Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2014-10-14 |
| 8232659 | Three dimensional IC device and alignment methods of IC device substrates | Chine-Gie Lou, Su Chen Fan | 2012-07-31 |
| 7952453 | Structure design for minimizing on-chip interconnect inductance | Hsien-Wei Chen, Shin-Puu Jeng | 2011-05-31 |
| 7834351 | Semiconductor device | Hsien-Wei Chen, Shih-Hsun Hsu | 2010-11-16 |
| 7803713 | Method for fabricating air gap for semiconductor device | Hsien-Wei Chen, Shin-Puu Jeng | 2010-09-28 |
| 7781892 | Interconnect structure and method of fabricating same | Chine-Gie Lou, Ping Liu, Su Chen Fan | 2010-08-24 |
| 7714443 | Pad structure design with reduced density | Hsien-Wei Chen, Anbiarshy Wu, Shih-Hsun Hsu, Shang-Yun Hou, Shin-Puu Jeng | 2010-05-11 |
| 7705696 | Structure design for minimizing on-chip interconnect inductance | Hsien-Wei Chen, Shin-Puu Jeng | 2010-04-27 |
| 7651893 | Metal electrical fuse structure | Hao-Yi Tsai, Hsien-Wei Chen, Shin-Puu Jeng, Shang-Yun Hou | 2010-01-26 |
| 7615841 | Design structure for coupling noise prevention | Hsien-Wei Chen | 2009-11-10 |
| 7553736 | Increasing dielectric constant in local regions for the formation of capacitors | Hsien-Wei Chen, Hao-Yi Tsai | 2009-06-30 |
| 7538346 | Semiconductor device | Hsien-Wei Chen, Shih-Hsun Hsu | 2009-05-26 |
| 7512924 | Semiconductor device structure and methods of manufacturing the same | Hsien-Wei Chen, Yi-Lung Cheng, Shin-Puu Jeng | 2009-03-31 |
| 7371663 | Three dimensional IC device and alignment methods of IC device substrates | Chine-Gie Lou, Su Chen Fan | 2008-05-13 |
| 7348672 | Interconnects with improved reliability | Hsien-Wei Chen, Shin-Puu Jeng | 2008-03-25 |
| 7301239 | Wiring structure to minimize stress induced void formation | Chien-Jung Wang, Su Chen Fan, Ding-Da Hu | 2007-11-27 |
| 7235424 | Method and apparatus for enhanced CMP planarization using surrounded dummy design | Hsien-Wei Chen, Hao-Yi Tsai, Shin-Puu Jeng, Jian-Hong Lin, Chih-Tao Lin +1 more | 2007-06-26 |
| 6930038 | Dual damascene partial gap fill polymer fabrication process | Chingfu Lin | 2005-08-16 |
| 6806182 | Method for eliminating via resistance shift in organic ILD | Darryl D. Restaino, Shahab Siddiqui, Erdem Kaltalioglu, Delores Bennett, Chih-Chih Liu +3 more | 2004-10-19 |
| 6797190 | Wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same | Chia-Lin Hsu, Art Yu, Shih-Hsun Hsu | 2004-09-28 |
| 6750129 | Process for forming fusible links | Gwo-Shii Yang, Jen-Kon Chen, Hans-Joachim Barth, Chiung-Sheng Hsiung, Chih-Chien Liu +3 more | 2004-06-15 |