Issued Patents All Time
Showing 51–75 of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10741751 | Fully aligned semiconductor device with a skip-level via | Nicholas Anthony Lanzillo, Benjamin D. Briggs, Chih-Chao Yang, Lawrence A. Clevenger | 2020-08-11 |
| 10714389 | Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration | James J. Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger | 2020-07-14 |
| 10651046 | Multiple patterning with late lithographically-defined mandrel cuts | Brendan O'Brien, Martin O'Toole, Keith Donegan | 2020-05-12 |
| 10615027 | Stack viabar structures | Su Chen Fan, Yann Mignot, James J. Kelly, Terence B. Hook | 2020-04-07 |
| 10573520 | Multiple patterning scheme integration with planarized cut patterning | Yongan Xu, Lawrence A. Clevenger, Yann Mignot, Cornelius Brown Peethala | 2020-02-25 |
| 10566231 | Interconnect formation with chamferless via, and related interconnect | Martin O'Toole, Christopher J. Penny, Jae-ouk Choo, Adam L. da Silva, Craig Child +3 more | 2020-02-18 |
| 10553789 | Fully aligned semiconductor device with a skip-level via | Nicholas Anthony Lanzillo, Benjamin D. Briggs, Chih-Chao Yang, Lawrence A. Clevenger | 2020-02-04 |
| 10546743 | Advanced interconnect with air gap | John H. Zhang, Yann Mignot, Lawrence A. Clevenger, Carl Radens, Richard S. Wise +2 more | 2020-01-28 |
| 10395941 | SADP method with mandrel undercut spacer portion for mandrel space dimension control | Ravi Prakash Srivastava | 2019-08-27 |
| 10361116 | Design-aware pattern density control in directed self-assembly graphoepitaxy process | Cheng Chi, Lin Hu, Kafai Lai, Chi-Chun Liu, Jed W. Pitera | 2019-07-23 |
| 10340180 | Merge mandrel features | Martin O'Toole, Terry A. Spooner, Jason E. Stephens | 2019-07-02 |
| 10276434 | Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration | James J. Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger | 2019-04-30 |
| 10168075 | Critical dimension shrink through selective metal growth on metal hardmask sidewalls | Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin | 2019-01-01 |
| 10032633 | Image transfer using EUV lithographic structure and double patterning process | Yann Mignot, Yongan Xu | 2018-07-24 |
| 9984920 | Design-aware pattern density control in directed self-assembly graphoepitaxy process | Cheng Chi, Lin Hu, Kafai Lai, Chi-Chun Liu, Jed W. Pitera | 2018-05-29 |
| 9953916 | Critical dimension shrink through selective metal growth on metal hardmask sidewalls | Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin | 2018-04-24 |
| 9953915 | Electrically conductive interconnect including via having increased contact surface area | James J. Demarest, Sean Teehan, Chih-Chao Yang | 2018-04-24 |
| 9842805 | Drive-in Mn before copper plating | Chih-Chao Yang | 2017-12-12 |
| 9716038 | Critical dimension shrink through selective metal growth on metal hardmask sidewalls | Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin | 2017-07-25 |
| 9653571 | Freestanding spacer having sub-lithographic lateral dimension and method of forming same | Su Chen Fan, Dong-Kwon Kim, Sean Lian, Fee Li Lie, Linus Jang | 2017-05-16 |
| 9595473 | Critical dimension shrink through selective metal growth on metal hardmask sidewalls | Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin | 2017-03-14 |
| 9576901 | Contact area structure and method for manufacturing the same | Su Chen Fan, Chih-Chao Yang | 2017-02-21 |
| 9553044 | Electrically conductive interconnect including via having increased contact surface area | James J. Demarest, Sean Teehan, Chih-Chao Yang | 2017-01-24 |
| 9385123 | STI region for small fin pitch in FinFET devices | Su Chen Fan, Chiahsun Tseng, Chun-Chen Yeh | 2016-07-05 |
| 9330965 | Double self aligned via patterning | Yongan Xu, Yunpeng Yin, Ailian Zhao | 2016-05-03 |