Issued Patents All Time
Showing 51–75 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8513085 | Structure and method to improve threshold voltage of MOSFETs including a high k dielectric | Sunfei Fang, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang | 2013-08-20 |
| 8476706 | CMOS having a SiC/SiGe alloy stack | Dureseti Chidambarrao, Yue Liang, Xiaojun Yu | 2013-07-02 |
| 8466496 | Selective partial gate stack for improved device isolation | Xiaojun Yu, Dureseti Chidambarrao, Yue Liang | 2013-06-18 |
| 8420468 | Strain-compensated field effect transistor and associated method of forming the transistor | Alberto Escobar, Edward J. Nowak | 2013-04-16 |
| 8354309 | Method of providing threshold voltage adjustment through gate dielectric stack modification | Michael P. Chudzik, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski +3 more | 2013-01-15 |
| 8236661 | Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage | Robert H. Dennard, Zhibin Ren, Xinlin Wang | 2012-08-07 |
| 8222673 | Self-aligned embedded SiGe structure and method of manufacturing the same | William K. Henson, Judson R. Holt, Michael D. Steigerwalt, Kuldeep Amarnath, Rohit Pal +1 more | 2012-07-17 |
| 8217470 | Field effect device including recessed and aligned germanium containing channel | Xiangdong Chen, Haining Yang | 2012-07-10 |
| 8173531 | Structure and method to improve threshold voltage of MOSFETS including a high K dielectric | Sunfei Fang, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang | 2012-05-08 |
| 8115254 | Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same | Huilong Zhu, Dureseti Chidambarrao, Gregory G. Freeman | 2012-02-14 |
| 8106455 | Threshold voltage adjustment through gate dielectric stack modification | Michael P. Chudzik, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski +3 more | 2012-01-31 |
| 8039331 | Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors | Scott D. Allen, Cyril Cabral, Jr., Kevin K. Dezfulian, Sunfei Fang, Rajarao Jammy +6 more | 2011-10-18 |
| 8030687 | Field effect transistor incorporating at least one structure for imparting temperature-dependent strain on the channel region and associated method of forming the transistor | Alberto Escobar, Edward J. Nowak | 2011-10-04 |
| 7989298 | Transistor having V-shaped embedded stressor | Kevin K. Chan, Judson R. Holt, Jeffrey B. Johnson, Thomas S. Kanarsky, Jophy Stephen Koshy +4 more | 2011-08-02 |
| 7977185 | Method and apparatus for post silicide spacer removal | Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim +1 more | 2011-07-12 |
| 7943467 | Structure and method to fabricate MOSFET with short gate | Huilong Zhu, Yanfeng Wang, Daewon Yang | 2011-05-17 |
| 7939413 | Embedded stressor structure and process | Yung Fu Chong, Zhijiong Luo, Joo-chan Kim, Kern Rim | 2011-05-10 |
| 7928436 | Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods | Kangguo Cheng, Jack A. Mandelman | 2011-04-19 |
| 7883948 | Method and structure for reducing induced mechanical stresses | Rajesh Rengarajan | 2011-02-08 |
| 7843024 | Method and structure for improving device performance variation in dual stress liner technology | Dureseti Chidambarrao | 2010-11-30 |
| 7842940 | Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost | Joel P. de Souza, Keith E. Fogel, Devendra K. Sadana, Haining Yang | 2010-11-30 |
| 7833873 | Method and structure to reduce contact resistance on thin silicon-on-insulator device | Louis L. Hsu, Jack A. Mandelman, Chun-Yung Sung | 2010-11-16 |
| 7812397 | Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof | Changguo Cheng, Dureseti Chidambarrao, Jack A. Mandelman, Kern Rim | 2010-10-12 |
| 7790553 | Methods for forming high performance gates and structures thereof | Huilong Zhu, Xiaomeng Chen, Mahender Kumar, Bachir Dirahoui, Jay William Strane +1 more | 2010-09-07 |
| 7767541 | Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods | Kangguo Cheng, Jack A. Mandelman | 2010-08-03 |