Issued Patents All Time
Showing 76–99 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7759739 | Transistor with dielectric stressor elements | Dureseti Chidambarrao, Kern Rim | 2010-07-20 |
| 7687865 | Method and structure to reduce contact resistance on thin silicon-on-insulator device | Louis L. Hsu, Jack A. Mandelman, Chun-Yung Sung | 2010-03-30 |
| 7659581 | Transistor with dielectric stressor element fully underlying the active semiconductor region | Dureseti Chidambarrao, Kern Rim | 2010-02-09 |
| 7659157 | Dual metal gate finFETs with single or dual high-K gate dielectric | Mahender Kumar | 2010-02-09 |
| 7572689 | Method and structure for reducing induced mechanical stresses | Rajesh Rengarajan | 2009-08-11 |
| 7542330 | SRAM with asymmetrical pass gates | Chun-Yung Sung, Clement Wann, Robert C. Wong, Ying Zhang | 2009-06-02 |
| 7538339 | Scalable strained FET device and method of fabricating the same | Sameer H. Jain, William K. Henson | 2009-05-26 |
| 7534667 | Structure and method for fabrication of deep junction silicon-on-insulator transistors | Dureseti Chidambarrao, John J. Ellis-Monaghan | 2009-05-19 |
| 7507631 | Epitaxial filled deep trench structures | Judson R. Holt | 2009-03-24 |
| 7501651 | Test structure of semiconductor device | Min-Chul Sun, Ja-Hum Ku, Manfred Eller, Roman Knoefler, Zhijiong Luo | 2009-03-10 |
| 7479437 | Method to reduce contact resistance on thin silicon-on-insulator device | Louis L. Hsu, Jack A. Mandelman, Chun-Yung Sung | 2009-01-20 |
| 7476938 | Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress | Dureseti Chidambarrao, Kern Rim | 2009-01-13 |
| 7462522 | Method and structure for improving device performance variation in dual stress liner technology | Dureseti Chidambarrao | 2008-12-09 |
| 7449378 | Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regions | Dureseti Chidambarrao | 2008-11-11 |
| 7449374 | Methods of manufacturing semiconductor devices with rotated substrates | Matthias Hierlemann, Chun-Yung Sung, Manfred Eller | 2008-11-11 |
| 7442618 | Method to engineer etch profiles in Si substrate for advanced semiconductor devices | Yung Fu Chong, Siddhartha Panda, Nivo Rovedo | 2008-10-28 |
| 7410852 | Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors | Scott D. Allen, Cyril Cabral, Jr., Kevin K. Dezfulian, Sunfei Fang, Rajarao Jammy +6 more | 2008-08-12 |
| 7405131 | Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor | Yung Fu Chong | 2008-07-29 |
| 7365399 | Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost | Joel P. de Souza, Keith E. Fogel, Devendra K. Sadana, Haining Yang | 2008-04-29 |
| 7358551 | Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions | Dureseti Chidambarrao | 2008-04-15 |
| 7317204 | Test structure of semiconductor device | Min-Chul Sun, Ja-Hum Ku, Manfred Eller, Wee Lang Tan, Sunfei Fang +1 more | 2008-01-08 |
| 7205639 | Semiconductor devices with rotated substrates and methods of manufacture thereof | Matthias Hierlemann, Chun-Yung Sung, Manfred Eller | 2007-04-17 |
| 7132322 | Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device | Kern Rim, Clement Wann | 2006-11-07 |
| 7002209 | MOSFET structure with high mechanical stress in the channel | Xiangdong Chen, Dureseti Chidambarrao, Oleg Gluschenkov, Kern Rim, Haining Yang | 2006-02-21 |