Issued Patents All Time
Showing 26–50 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9379185 | Method of forming channel region dopant control in fin field effect transistor | Murshed Chowdhury, Arvind Kumar | 2016-06-28 |
| 9349609 | Semiconductor process temperature optimization | Yue Liang, Xiaojun Yu | 2016-05-24 |
| 9337338 | Tucked active region without dummy poly for performance boost and variation reduction | Yue Liang, Xiaojun Yu | 2016-05-10 |
| 9312274 | Merged fin structures for finFET devices | Andres Bryant, Jeffrey B. Johnson, Mickey H. Yu | 2016-04-12 |
| 9305999 | Stress-generating structure for semiconductor-on-insulator devices | Huilong Zhu, Dureseti Chidambarrao, Gregory G. Freeman | 2016-04-05 |
| 9299780 | Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device | Arvind Kumar, Dan M. Mocuta | 2016-03-29 |
| 9252215 | Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device | Arvind Kumar, Dan M. Mocuta | 2016-02-02 |
| 9171954 | FinFET structure and method to adjust threshold voltage in a FinFET structure | Eduard A. Cartier, Dechao Guo, Gan Wang, Yanfeng Wang, Keith Kwong Hon Wong | 2015-10-27 |
| 9105722 | Tucked active region without dummy poly for performance boost and variation reduction | Yue Liang, Xiaojun Yu | 2015-08-11 |
| 9093275 | Multi-height multi-composition semiconductor fins | Augustin J. Hong, Byeong Y. Kim, Dan M. Mocuta | 2015-07-28 |
| 9082877 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Yue Liang, Dureseti Chidambarrao, William K. Henson, Unoh Kwon, Shreesh Narasimha +1 more | 2015-07-14 |
| 8993389 | Dummy gate interconnect for semiconductor device | Yue Liang, Xiaojun Yu | 2015-03-31 |
| 8941189 | Fin-shaped field effect transistor (finFET) structures having multiple threshold voltages (Vt) and method of forming | Murshed Chowdhury, Benjamin Cipriany, Arvind Kumar | 2015-01-27 |
| 8932949 | FinFET structure and method to adjust threshold voltage in a FinFET structure | Eduard A. Cartier, Dechao Guo, Gan Wang, Yanfeng Wang, Keith Kwong Hon Wong | 2015-01-13 |
| 8927427 | Anticipatory implant for TSV | Troy L. Graves-Abe, Chandrasekharan Kothandaraman | 2015-01-06 |
| 8853035 | Tucked active region without dummy poly for performance boost and variation reduction | Xiaojun Yu, Yue Liang | 2014-10-07 |
| 8835234 | MOS having a sic/sige alloy stack | Dureseti Chidambarrao, Yue Liang, Xiaojun Yu | 2014-09-16 |
| 8803243 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Yue Liang, Dureseti Chidambarrao, William K. Henson, Unoh Kwon, Shreesh Narasimha +1 more | 2014-08-12 |
| 8796771 | Creating anisotropically diffused junctions in field effect transistor devices | Jeffrey B. Johnson, Qingqing Liang, Edward P. Maciejewski | 2014-08-05 |
| 8785291 | Post-gate shallow trench isolation structure formation | Xiaojun Yu, Yue Liang | 2014-07-22 |
| 8779469 | Post-gate shallow trench isolation structure formation | Yue Liang, Xiaojun Yu | 2014-07-15 |
| 8772149 | FinFET structure and method to adjust threshold voltage in a FinFET structure | Eduard A. Cartier, Dechao Guo, Gan Wang, Yanfeng Wang, Keith Kwong Hon Wong | 2014-07-08 |
| 8633096 | Creating anisotropically diffused junctions in field effect transistor devices | Jeffrey B. Johnson, Qingqing Liang, Edward P. Maciejewski | 2014-01-21 |
| 8629501 | Stress-generating structure for semiconductor-on-insulator devices | Huilong Zhu, Dureseti Chidambarrao, Gregory G. Freeman | 2014-01-14 |
| 8598009 | Self-aligned embedded SiGe structure and method of manufacturing the same | William K. Henson, Judson R. Holt, Michael D. Steigerwalt, Kuldeep Amarnath, Rohit Pal +1 more | 2013-12-03 |