Issued Patents 2023
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854955 | Fan-out package with controllable standoff | Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2023-12-26 |
| 11855059 | Fan-out package with cavity substrate | Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin | 2023-12-26 |
| 11855047 | Chip package structure with conductive shielding film | Chen-Hua Yu, An-Jhih Su, Jing-Cheng Lin | 2023-12-26 |
| 11855028 | Hybrid micro-bump integration with redistribution layer | Ting-Li Yang, Yi-Wen Wu, Sheng-Pin Yang, Hao-Chun Liu | 2023-12-26 |
| 11855017 | Semiconductor device and method | Ting-Li Yang, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang | 2023-12-26 |
| 11854998 | Semiconductor device and method of manufacture | Jing-Cheng Lin, Chen-Hua Yu | 2023-12-26 |
| 11854964 | Structure and formation method of semiconductor device with conductive bumps | Ming-Da Cheng, Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Yung-Sheng Lin | 2023-12-26 |
| 11848265 | Semiconductor package with improved interposer structure | Yi-Wen Wu, Techi Wong, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng | 2023-12-19 |
| 11837587 | Package structure and manufacturing method thereof | Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang +2 more | 2023-12-05 |
| 11824007 | Dual-sided routing in 3D SiP structure | Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong | 2023-11-21 |
| 11817437 | Method of forming package structure | Jing-Cheng Lin | 2023-11-14 |
| 11817413 | Semiconductor package structure comprising via structure and redistribution layer structure and method for forming the same | Neng-Chieh CHANG, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu | 2023-11-14 |
| 11784148 | Semiconductor package | Chia-Kuei Hsu, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng | 2023-10-10 |
| 11776935 | Semiconductor device and method of manufacture | Jing-Cheng Lin, Chen-Hua Yu | 2023-10-03 |
| 11764159 | Package with fan-out structures | Shin-Puu Jeng, Po-Yao Chuang, Techi Wong | 2023-09-19 |
| 11764139 | Semiconductor device and method | Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu | 2023-09-19 |
| 11756802 | Thermally conductive material in the recess of an encapsulant and sidewall of an integrated circuit device | Jing-Cheng Lin, Li-Hui Cheng | 2023-09-12 |
| 11682599 | Chip package structure with molding layer and method for forming the same | Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2023-06-20 |
| 11670577 | Chip package with redistribution structure having multiple chips | Shin-Puu Jeng, Po-Yao Chuang, Feng-Cheng Hsu, Shuo-Mao Chen, Techi Wong | 2023-06-06 |
| 11646256 | Heterogeneous fan-out structure and method of manufacture | Po-Yao Chuang, Shin-Puu Jeng, Techi Wong | 2023-05-09 |
| 11610854 | Semiconductor device and method of manufacture | Po-Yao Chuang, Ming-Chih Yew, Shin-Puu Jeng | 2023-03-21 |
| 11605579 | Semiconductor device having passivation layer and method of manufacturing the same | Jing-Cheng Lin, Li-Hui Cheng | 2023-03-14 |
| 11600573 | Structure and formation method of chip package with conductive support elements to reduce warpage | Techi Wong, Yi-Wen Wu, Po-Yao Chuang, Shin-Puu Jeng | 2023-03-07 |
| 11600575 | Method for forming chip package structure | Shin-Puu Jeng, Techi Wong, Po-Yao Lin, Ming-Chih Yew, Po-Yao Chuang | 2023-03-07 |
| 11594508 | Redistribution lines having nano columns and method forming same | Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu, Kai-Di Wu, Su-Fei Lin | 2023-02-28 |