Issued Patents 2023
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11855059 | Fan-out package with cavity substrate | Po-Hao Tsai, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin | 2023-12-26 |
| 11854955 | Fan-out package with controllable standoff | Po-Hao Tsai, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2023-12-26 |
| 11848265 | Semiconductor package with improved interposer structure | Yi-Wen Wu, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng | 2023-12-19 |
| 11824007 | Dual-sided routing in 3D SiP structure | Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng | 2023-11-21 |
| 11764159 | Package with fan-out structures | Shin-Puu Jeng, Po-Hao Tsai, Po-Yao Chuang | 2023-09-19 |
| 11682599 | Chip package structure with molding layer and method for forming the same | Po-Hao Tsai, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2023-06-20 |
| 11670577 | Chip package with redistribution structure having multiple chips | Shin-Puu Jeng, Po-Hao Tsai, Po-Yao Chuang, Feng-Cheng Hsu, Shuo-Mao Chen | 2023-06-06 |
| 11646256 | Heterogeneous fan-out structure and method of manufacture | Po-Hao Tsai, Po-Yao Chuang, Shin-Puu Jeng | 2023-05-09 |
| 11600573 | Structure and formation method of chip package with conductive support elements to reduce warpage | Po-Hao Tsai, Yi-Wen Wu, Po-Yao Chuang, Shin-Puu Jeng | 2023-03-07 |
| 11600575 | Method for forming chip package structure | Shin-Puu Jeng, Po-Yao Lin, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Chuang | 2023-03-07 |