PC

Po-Yao Chuang

TSMC: 14 patents #172 of 4,064Top 5%
Overall (2023): #4,029 of 537,848Top 1%
14
Patents 2023

Issued Patents 2023

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDate
11855059 Fan-out package with cavity substrate Po-Hao Tsai, Techi Wong, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin 2023-12-26
11854955 Fan-out package with controllable standoff Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Shin-Puu Jeng 2023-12-26
11848305 Semiconductor packages including passive devices and methods of forming same Shin-Puu Jeng, Shuo-Mao Chen 2023-12-19
11848265 Semiconductor package with improved interposer structure Yi-Wen Wu, Techi Wong, Po-Hao Tsai, Shih-Ting Hung, Shin-Puu Jeng 2023-12-19
11824007 Dual-sided routing in 3D SiP structure Po-Hao Tsai, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong 2023-11-21
11804451 Package structure and method of fabricating the same Yi-Wen Wu, Shin-Puu Jeng, Shih-Ting Hung 2023-10-31
11764159 Package with fan-out structures Shin-Puu Jeng, Po-Hao Tsai, Techi Wong 2023-09-19
11682599 Chip package structure with molding layer and method for forming the same Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Shin-Puu Jeng 2023-06-20
11670577 Chip package with redistribution structure having multiple chips Shin-Puu Jeng, Po-Hao Tsai, Feng-Cheng Hsu, Shuo-Mao Chen, Techi Wong 2023-06-06
11646256 Heterogeneous fan-out structure and method of manufacture Po-Hao Tsai, Shin-Puu Jeng, Techi Wong 2023-05-09
11637054 Semiconductor package and method of manufacturing the same Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Yi-Wen Wu 2023-04-25
11610854 Semiconductor device and method of manufacture Po-Hao Tsai, Ming-Chih Yew, Shin-Puu Jeng 2023-03-21
11600573 Structure and formation method of chip package with conductive support elements to reduce warpage Po-Hao Tsai, Techi Wong, Yi-Wen Wu, Shin-Puu Jeng 2023-03-07
11600575 Method for forming chip package structure Shin-Puu Jeng, Techi Wong, Po-Yao Lin, Ming-Chih Yew, Po-Hao Tsai 2023-03-07