Issued Patents 2021
Showing 51–75 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11004736 | Integrated circuit having a single damascene wiring network | Hsueh-Chung Chen, Junli Wang, Somnath Ghosh, Chih-Chao Yang | 2021-05-11 |
| 11004790 | Method of manufacturing an interconnect without dielectric exclusion zones by thermal decomposition of a sacrificial filler material | Benjamin D. Briggs, Christopher J. Penny, Michael Rizzolo | 2021-05-11 |
| 10998193 | Spacer-assisted lithographic double patterning | Timothy Mathew Philip, Somnath Ghosh, Daniel James Dechene, Robert R. Robison | 2021-05-04 |
| 10991619 | Top via process accounting for misalignment by increasing reliability | Chen Zhang, Benjamin D. Briggs, Brent A. Anderson, Chih-Chao Yang | 2021-04-27 |
| 10985063 | Semiconductor device with local connection | Kangguo Cheng, Carl Radens, Junli Wang, John H. Zhang | 2021-04-20 |
| 10978393 | Hybrid dielectric scheme for varying liner thickness and manganese concentration | Benjamin D. Briggs, Nicholas Anthony Lanzillo, Takeshi Nogami, Christopher J. Penny, Michael Rizzolo | 2021-04-13 |
| 10978343 | Interconnect structure having fully aligned vias | Chanro Park, Nicholas Anthony Lanzillo, Christopher J. Penny, Balasubramanian Pranatharthiharan | 2021-04-13 |
| 10971030 | Remote physical training | Benjamin D. Briggs, Leigh Anne H. Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis Sipolins | 2021-04-06 |
| 10964588 | Selective ILD deposition for fully aligned via with airgap | Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Michael Rizzolo, Hosadurga Shobha | 2021-03-30 |
| 10957582 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Michael Rizzolo, Terry A. Spooner, Theodorus E. Standaert | 2021-03-23 |
| 10957646 | Hybrid BEOL metallization utilizing selective reflection mask | Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Gen Tsutsui +2 more | 2021-03-23 |
| 10957583 | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs | Sean D. Burns, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot, Christopher J. Penny +2 more | 2021-03-23 |
| 10957581 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Michael Rizzolo, Terry A. Spooner, Theodorus E. Standaert | 2021-03-23 |
| 10950722 | Vertical gate all-around transistor | John H. Zhang, Carl Radens, Yiheng Xu | 2021-03-16 |
| 10950787 | Method having resistive memory crossbar array employing selective barrier layer growth | Takashi Ando, Chih-Chao Yang | 2021-03-16 |
| 10950662 | Resistive memory device with meshed electrodes | Takashi Ando, Chih-Chao Yang, Michael Rizzolo | 2021-03-16 |
| 10943972 | Precision BEOL resistors | Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang | 2021-03-09 |
| 10943866 | Method and structure to construct cylindrical interconnects to reduce resistance | Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Hosadurga Shobha | 2021-03-09 |
| 10937653 | Multiple patterning scheme integration with planarized cut patterning | Hsueh-Chung Chen, Yongan Xu, Yann Mignot, Cornelius Brown Peethala | 2021-03-02 |
| 10936782 | Semiconductor process modeling to enable skip via in place and route flow | Dongbing Shao, Zheng Xu | 2021-03-02 |
| 10930553 | Forming self-aligned vias and air-gaps in semiconductor fabrication | Carl Radens, John H. Zhang | 2021-02-23 |
| 10923575 | Low resistance contact for transistors | Junli Wang, Kirk D. Peterson, Baozhen Li, Terry A. Spooner, John E. Sheets, II | 2021-02-16 |
| 10912986 | Dynamic rigidity mechanism | Benjamin D. Briggs, Bartlet H. DeProspo, Michael Rizzolo | 2021-02-09 |
| 10916699 | Resistive memory crossbar array employing selective barrier layer growth | Takashi Ando, Chih-Chao Yang | 2021-02-09 |
| 10916501 | Back end of line electrical fuse structure and method of fabrication | Benjamin D. Briggs, Michael Rizzolo, Chih-Chao Yang | 2021-02-09 |