Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
MR

Michael Rizzolo

IBM: 37 patents #54 of 11,638Top 1%
TETessera: 2 patents #11 of 70Top 20%
Albany, NY: #2 of 160 inventorsTop 2%
New York: #23 of 12,766 inventorsTop 1%
Overall (2021): #445 of 548,734Top 1%
39 Patents 2021

Issued Patents 2021

Showing 1–25 of 39 patents

Patent #TitleCo-InventorsDate
11195993 Encapsulation topography-assisted self-aligned MRAM top contact Nicholas Anthony Lanzillo, Benjamin D. Briggs, Lawrence A. Clevenger 2021-12-07
11177437 Alignment through topography on intermediate component for memory device patterning Hao Tang, Injo Ok, Theodorus E. Standaert 2021-11-16
11164779 Bamboo tall via interconnect structures Chih-Chao Yang, Theodorus E. Standaert 2021-11-02
11164377 Motion-controlled portals in virtual reality Aldis Sipolins, Lawrence A. Clevenger, Benjamin D. Briggs, Christopher J. Penny, Patrick Watson 2021-11-02
11158584 Selective CVD alignment-mark topography assist for non-volatile memory Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs 2021-10-26
11138890 Secure access for drone package delivery Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Aldis Sipolins 2021-10-05
11132712 Method for using 3D positional spatial olfaction for virtual marketing Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christoper J. Penny, Aldis Sipolins 2021-09-28
11121174 MRAM integration into the MOL for fast 1T1M cells Alexander Reznicek, Ruilong Xie 2021-09-14
11121173 Preserving underlying dielectric layer during MRAM device formation Ashim Dutta 2021-09-14
11081643 Bevel metal removal using ion beam etch Ashim Dutta, Saba Zare, Theodorus E. Standaert, Daniel C. Edelstein 2021-08-03
11074387 Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance Prasad Bhosale, Chih-Chao Yang 2021-07-27
11069854 Laser anneal for MRAM encapsulation enhancement Oscar van der Straten, Alexander Reznicek, Oleg Gluschenkov 2021-07-20
11063089 Resistive memory device with meshed electrodes Takashi Ando, Lawrence A. Clevenger, Chih-Chao Yang 2021-07-13
11056429 Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny 2021-07-06
11049744 Optimizing semiconductor binning by feed-forward process adjustment Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Theodorus E. Standaert, James H. Stathis 2021-06-29
11031250 Semiconductor structures of more uniform thickness Mona A. Ebrish, Son V. Nguyen, Raghuveer R. Patlolla, Donald F. Canaperi 2021-06-08
11031542 Contact via with pillar of alternating layers Chih-Chao Yang, Daniel C. Edelstein, Theodorus E. Standaert 2021-06-08
11018090 Selective CVD alignment-mark topography assist for non-volatile memory Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs 2021-05-25
11004735 Conductive interconnect having a semi-liner and no top surface recess Cornelius Brown Peethala, Oscar van der Straten, Chih-Chao Yang 2021-05-11
11004790 Method of manufacturing an interconnect without dielectric exclusion zones by thermal decomposition of a sacrificial filler material Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny 2021-05-11
10978393 Hybrid dielectric scheme for varying liner thickness and manganese concentration Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Takeshi Nogami, Christopher J. Penny 2021-04-13
10978388 Skip via for metal interconnects Hari Prasad Amanapu, Prasad Bhosale, Nicholas V. LiCausi, Lars Liebmann, James Jay McMahon +1 more 2021-04-13
10971030 Remote physical training Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Aldis Sipolins 2021-04-06
10964588 Selective ILD deposition for fully aligned via with airgap Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha 2021-03-30
10957581 Self aligned via and pillar cut for at least a self aligned double pitch Benjamin D. Briggs, Lawrence A. Clevenger, Terry A. Spooner, Theodorus E. Standaert 2021-03-23