Issued Patents 2021
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11189693 | Transistor having reduced contact resistance | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2021-11-30 |
| 11177437 | Alignment through topography on intermediate component for memory device patterning | Hao Tang, Michael Rizzolo, Injo Ok | 2021-11-16 |
| 11164779 | Bamboo tall via interconnect structures | Chih-Chao Yang, Michael Rizzolo | 2021-11-02 |
| 11145658 | Semiconductor structures with deep trench capacitor and methods of manufacture | Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung +1 more | 2021-10-12 |
| 11145813 | Bottom electrode for semiconductor memory device | Chih-Chao Yang, Daniel C. Edelstein | 2021-10-12 |
| 11121032 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2021-09-14 |
| 11081643 | Bevel metal removal using ion beam etch | Ashim Dutta, Saba Zare, Michael Rizzolo, Daniel C. Edelstein | 2021-08-03 |
| 11056493 | Semiconductor structures with deep trench capacitor and methods of manufacture | Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Effendi Leobandung +1 more | 2021-07-06 |
| 11049744 | Optimizing semiconductor binning by feed-forward process adjustment | Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Michael Rizzolo, James H. Stathis | 2021-06-29 |
| 11031542 | Contact via with pillar of alternating layers | Chih-Chao Yang, Daniel C. Edelstein, Michael Rizzolo | 2021-06-08 |
| 10998230 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2021-05-04 |
| 10998227 | Metal insulator metal capacitor with extended capacitor plates | Chih-Chao Yang | 2021-05-04 |
| 10985056 | Structure and method to improve FAV RIE process margin and Electromigration | Benjamin D. Briggs, Joe Lee | 2021-04-20 |
| 10971601 | Replacement metal gate structures | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2021-04-06 |
| 10971398 | Cobalt interconnect structure including noble metal layer | Chih-Chao Yang | 2021-04-06 |
| 10957581 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Terry A. Spooner | 2021-03-23 |
| 10957584 | Structure and method to improve FAV RIE process margin and electromigration | Benjamin D. Briggs, Joe Lee | 2021-03-23 |
| 10957582 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Terry A. Spooner | 2021-03-23 |
| 10930754 | Replacement metal gate structures | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2021-02-23 |
| 10916660 | Vertical transistor with a body contact for back-biasing | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2021-02-09 |
| 10903338 | Vertical FET with shaped spacer to reduce parasitic capacitance | Junli Wang, Kangguo Cheng, Veeraraghavan S. Basker | 2021-01-26 |
| 10892404 | Sacrificial buffer layer for metal removal at a bevel edge of a substrate | Ashim Dutta, Saba Zare, Michael Rizzolo, Daniel C. Edelstein | 2021-01-12 |