Issued Patents 2021
Showing 1–25 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11205723 | Selective source/drain recess for improved performance, isolation, and scaling | Ardasheir Rahman, Brent A. Anderson, Stuart A. Sieg, Christopher J. Waskiewicz | 2021-12-21 |
| 11195745 | Forming single and double diffusion breaks for fin field-effect transistor structures | Juntao Li, Kangguo Cheng, Ruilong Xie | 2021-12-07 |
| 11189725 | VTFET with cell height constraints | Heng Wu, Ruilong Xie, Lan Yu, Alexander Reznicek | 2021-11-30 |
| 11189693 | Transistor having reduced contact resistance | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2021-11-30 |
| 11183558 | Nanosheet transistor having partially self-limiting bottom isolation extending into the substrate and under the source/drain and gate regions | Chun-Chen Yeh, Veeraraghavan S. Basker, Alexander Reznicek | 2021-11-23 |
| 11177162 | Trapezoidal interconnect at tight BEOL pitch | Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Koichi Motoyama, Christopher J. Penny +1 more | 2021-11-16 |
| 11177132 | Self aligned block masks for implantation control | Romain Lallement, Ardasheir Rahman, Liying Jiang, Brent A. Anderson | 2021-11-16 |
| 11164792 | Complementary field-effect transistors | Ruilong Xie, Alexander Reznicek, Jingyun Zhang | 2021-11-02 |
| 11164778 | Barrier-free vertical interconnect structure | Hsueh-Chung Chen, Su Chen Fan, Yann Mignot, Lawrence A. Clevenger | 2021-11-02 |
| 11152307 | Buried local interconnect | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, John H. Zhang | 2021-10-19 |
| 11152257 | Barrier-less prefilled via formation | Nicholas Anthony Lanzillo, Hosadurga Shobha, Lawrence A. Clevenger, Christopher J. Penny, Robert R. Robison +1 more | 2021-10-19 |
| 11145550 | Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor | Brent A. Anderson, Albert M. Young | 2021-10-12 |
| 11145551 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Theodoras E. Standaert | 2021-10-12 |
| 11145543 | Semiconductor via structure with lower electrical resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner | 2021-10-12 |
| 11139385 | Interface-less contacts to source/drain regions and gate electrode over active portion of device | Veeraraghavan S. Basker, Huiming Bu | 2021-10-05 |
| 11121032 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2021-09-14 |
| 11107814 | Vertical fin field effect transistor devices with a replacement metal gate | Ruqiang Bao, Michael P. Belyansky | 2021-08-31 |
| 11101217 | Buried power rail for transistor devices | Ruilong Xie, Alexander Reznicek, Kangguo Cheng | 2021-08-24 |
| 11088278 | Precise junction placement in vertical semiconductor devices using etch stop layers | Huiming Bu, Liying Jiang, Siyuranga O. Koswatta | 2021-08-10 |
| 11075161 | Large via buffer | Yann Mignot, Hsueh-Chung Chen, Chi-Chun Liu, Mary Claire Silvestre | 2021-07-27 |
| 11062993 | Contacts having a geometry to reduce resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner | 2021-07-13 |
| 11062960 | Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices | Heng Wu, Kangguo Cheng, Zuoguang Liu | 2021-07-13 |
| 11056386 | Two-dimensional (2D) self-aligned contact (or via) to enable further device scaling | Veeraraghavan S. Basker, Chun-Chen Yeh, Alexander Reznicek | 2021-07-06 |
| 11049858 | Vertical fin field effect transistor devices with a replacement metal gate | Ruqiang Bao, Michael P. Belyansky | 2021-06-29 |
| 11024369 | Static random-access memory cell design | Lan Yu, Heng Wu, Ruqiang Bao, Dechao Guo | 2021-06-01 |