Issued Patents 2021
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211379 | Fabrication of field effect transistors with different threshold voltages through modified channel interfaces | Takashi Ando, Hemanth Jagannathan, Choonghyun Lee | 2021-12-28 |
| 11195929 | Conformal replacement gate electrode for short channel devices | Takashi Ando, Masanobu Hatanaka, Vijay Narayanan, Yohei Ogawa, John Rozen | 2021-12-07 |
| 11195762 | Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device | Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan | 2021-12-07 |
| 11189616 | Multi-threshold voltage non-planar complementary metal-oxtde-semiconductor devices | Koji Watanabe | 2021-11-30 |
| 11183427 | Differing device characteristics on a single wafer by selective etch | Huimei Zhou, Shogo Mochizuki, Gen Tsutsui | 2021-11-23 |
| 11177257 | Fabrication of field effect transistors with different threshold voltages through modified channel interfaces | Takashi Ando, Hemanth Jagannathan, Choonghyun Lee | 2021-11-16 |
| 11152489 | Additive core subtractive liner for metal cut etch processes | Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira Seshadri +1 more | 2021-10-19 |
| 11107814 | Vertical fin field effect transistor devices with a replacement metal gate | Junli Wang, Michael P. Belyansky | 2021-08-31 |
| 11094801 | Oxide isolated fin-type field-effect transistors | Hemanth Jagannathan, Paul C. Jamison, Choonghyun Lee | 2021-08-17 |
| 11075281 | Additive core subtractive liner for metal cut etch processes | Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira Seshadri +1 more | 2021-07-27 |
| 11049858 | Vertical fin field effect transistor devices with a replacement metal gate | Junli Wang, Michael P. Belyansky | 2021-06-29 |
| 11031301 | Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages | Unoh Kwon, Vijay Narayanan | 2021-06-08 |
| 11024369 | Static random-access memory cell design | Lan Yu, Junli Wang, Heng Wu, Dechao Guo | 2021-06-01 |
| 11024711 | Nanosheet FET bottom isolation | Zhenxing Bi, Kangguo Cheng, Zheng Xu | 2021-06-01 |
| 11011517 | Semiconductor structure including first FinFET devices for low power applications and second FinFET devices for high power applications | Lan Yu, Junli Wang, Heng Wu, Dechao Guo | 2021-05-18 |
| 11004850 | Vertical fin field effect transistor devices with a replacement metal gate | Junli Wang, Michael P. Belyansky | 2021-05-11 |
| 10985075 | Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages | Unoh Kwon, Vijay Narayanan | 2021-04-20 |
| 10971399 | Oxygen-free replacement liner for improved transistor performance | Heng Wu, Dechao Guo, Junli Wang | 2021-04-06 |
| 10971626 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Dechao Guo, Joel P. de Souza, Stephen W. Bedell, Shogo Mochizuki +3 more | 2021-04-06 |
| 10957646 | Hybrid BEOL metallization utilizing selective reflection mask | Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Gen Tsutsui +2 more | 2021-03-23 |
| 10957696 | Self-aligned metal gate with poly silicide for vertical transport field-effect transistors | Brent A. Anderson, Dechao Guo, Vijay Narayanan | 2021-03-23 |
| 10943989 | Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization | Heng Wu, Junli Wang, Lan Yu, Dechao Guo | 2021-03-09 |
| 10937648 | Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS | Choonghyun Lee, Gen Tsutsui, Dechao Guo | 2021-03-02 |
| 10930734 | Nanosheet FET bottom isolation | Zhenxing Bi, Kangguo Cheng, Zheng Xu | 2021-02-23 |
| 10903124 | Transistor structure with n/p boundary buffer | Romain Lallement, Indira Seshadri | 2021-01-26 |