Issued Patents 2021
Showing 25 most recent of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211462 | Using selectively formed cap layers to form self-aligned contacts to source/drain regions | Chanro Park, Kangguo Cheng, Ruilong Xie | 2021-12-28 |
| 11211379 | Fabrication of field effect transistors with different threshold voltages through modified channel interfaces | Takashi Ando, Ruqiang Bao, Hemanth Jagannathan | 2021-12-28 |
| 11205728 | Vertical field effect transistor with reduced parasitic capacitance | Alexander Reznicek, Xin Miao, Jingyun Zhang | 2021-12-21 |
| 11201092 | Gate channel length control in VFET | Injo Ok, Soon-Cheon Seo, Alexander Reznicek | 2021-12-14 |
| 11201241 | Vertical field effect transistor and method of manufacturing a vertical field effect transistor | Alexander Reznicek, Xin Miao, Richard Southwick | 2021-12-14 |
| 11195764 | Vertical transport field-effect transistors having germanium channel surfaces | Pouya Hashemi, Takashi Ando | 2021-12-07 |
| 11195912 | Inner spacer for nanosheet transistors | Kangguo Cheng, Juntao Li, Peng Xu | 2021-12-07 |
| 11189661 | FinFET 2T2R RRAM | Alexander Reznicek, Takashi Ando, Pouya Hashemi, Jingyun Zhang | 2021-11-30 |
| 11183430 | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors | Kangguo Cheng, Juntao Li, Peng Xu | 2021-11-23 |
| 11183577 | Formation of air gap spacers for reducing parasitic capacitance | Kangguo Cheng, Peng Xu, Heng Wu | 2021-11-23 |
| 11177257 | Fabrication of field effect transistors with different threshold voltages through modified channel interfaces | Takashi Ando, Ruqiang Bao, Hemanth Jagannathan | 2021-11-16 |
| 11165017 | Replacement bottom electrode structure process to form misalignment tolerate MRAM with high yield | Pouya Hashemi, Takashi Ando, Dimitri Houssameddine, Alexander Reznicek, Jingyun Zhang | 2021-11-02 |
| 11158715 | Vertical FET with asymmetric threshold voltage and channel thicknesses | Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek | 2021-10-26 |
| 11152510 | Long channel optimization for gate-all-around transistors | Jingyun Zhang, Takashi Ando, Pouya Hashemi, Alexander Reznicek | 2021-10-19 |
| 11145555 | Gate-last process for vertical transport field-effect transistor | Shogo Mochizuki, Hemanth Jagannathan | 2021-10-12 |
| 11139380 | Vertical fin-type bipolar junction transistor with self-aligned base contact | Seyoung Kim, Injo Ok, Soon-Cheon Seo | 2021-10-05 |
| 11133305 | Nanosheet P-type transistor with oxygen reservoir | Takashi Ando, Jingyun Zhang | 2021-09-28 |
| 11133309 | Multi-threshold voltage gate-all-around transistors | Jingyun Zhang, Takashi Ando | 2021-09-28 |
| 11121232 | Stacked nanosheets with self-aligned inner spacers and metallic source/drain | Kangguo Cheng, Juntao Li | 2021-09-14 |
| 11121218 | Gate-all-around transistor structure | Jingyun Zhang, Takashi Ando | 2021-09-14 |
| 11120991 | Lateral semiconductor nanotube with hexagonal shape | Juntao Li, Kangguo Cheng, Peng Xu | 2021-09-14 |
| 11101182 | Nanosheet transistors with different gate dielectrics and workfunction metals | Kangguo Cheng, Juntao Li, Peng Xu | 2021-08-24 |
| 11094801 | Oxide isolated fin-type field-effect transistors | Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison | 2021-08-17 |
| 11094883 | Structure and method to fabricate resistive memory with vertical pre-determined filament | Chanro Park, Kangguo Cheng, Ruilong Xie | 2021-08-17 |
| 11088139 | Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy | Jingyun Zhang, Takashi Ando, Alexander Reznicek, Pouya Hashemi | 2021-08-10 |