Issued Patents 2021
Showing 1–25 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211452 | Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts | Ruilong Xie, Reinaldo Vega, Kangguo Cheng, Juntao Li | 2021-12-28 |
| 11211462 | Using selectively formed cap layers to form self-aligned contacts to source/drain regions | Choonghyun Lee, Kangguo Cheng, Ruilong Xie | 2021-12-28 |
| 11205591 | Top via interconnect with self-aligned barrier layer | Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang | 2021-12-21 |
| 11201056 | Pitch multiplication with high pattern fidelity | Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang | 2021-12-14 |
| 11201112 | Fully-aligned skip-vias | Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang | 2021-12-14 |
| 11183561 | Nanosheet transistor with inner spacers | Kangguo Cheng, Ruilong Xie, Juntao Li | 2021-11-23 |
| 11183581 | Vertical field effect transistor having improved uniformity | Kangguo Cheng, Juntao Li, Ruilong Xie | 2021-11-23 |
| 11177163 | Top via structure with enlarged contact area with upper metallization level | Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang | 2021-11-16 |
| 11177170 | Removal of barrier and liner layers from a bottom of a via | Koichi Motoyama, Kenneth Chun Kuen Cheng, Nicholas Anthony Lanzillo | 2021-11-16 |
| 11177181 | Scalable device for FINFET technology | Ruilong Xie, Kangguo Cheng, Juntao Li | 2021-11-16 |
| 11177214 | Interconnects with hybrid metal conductors | Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang | 2021-11-16 |
| 11177632 | Augmented semiconductor lasers with spontaneous emissions blockage | Julien Frougier, Kangguo Cheng, Ruilong Xie | 2021-11-16 |
| 11171044 | Planarization controllability for interconnect structures | Ruilong Xie, Kangguo Cheng, Julien Frougier, Chih-Chao Yang | 2021-11-09 |
| 11164774 | Interconnects with spacer structure for forming air-gaps | Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang | 2021-11-02 |
| 11164793 | Reduced source/drain coupling for CFET | Ruilong Xie, Alexander Reznicek, Chun-Chen Yeh | 2021-11-02 |
| 11158544 | Vertical stacked nanosheet CMOS transistors with different work function metals | Kangguo Cheng, Juntao Li, Ruilong Xie | 2021-10-26 |
| 11139202 | Fully aligned top vias with replacement metal lines | Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang | 2021-10-05 |
| 11139399 | Vertical transistor with self-aligned gate | Juntao Li, Kangguo Cheng, Ruilong Xie | 2021-10-05 |
| 11133308 | Uniform work function metal recess for vertical transistor complementary metal oxide semiconductor technology | Ruilong Xie, Muthumanickam Sankarapandian, Kangguo Cheng | 2021-09-28 |
| 11131647 | Ion-sensitive field-effect transistor with sawtooth well to enhance sensitivity | Kangguo Cheng, Juntao Li, Ruilong Xie | 2021-09-28 |
| 11127676 | Removal or reduction of chamfer for fully-aligned via | Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang | 2021-09-21 |
| 11127825 | Middle-of-line contacts with varying contact area providing reduced contact resistance | Kangguo Cheng, Ruilong Xie, Hari Prasad Amanapu | 2021-09-21 |
| 11094590 | Structurally stable self-aligned subtractive vias | Sagarika Mukesh, Dominik Metzler, Timothy Mathew Philip | 2021-08-17 |
| 11094883 | Structure and method to fabricate resistive memory with vertical pre-determined filament | Kangguo Cheng, Ruilong Xie, Choonghyun Lee | 2021-08-17 |
| 11094580 | Structure and method to fabricate fully aligned via with reduced contact resistance | Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang | 2021-08-17 |