Issued Patents 2021
Showing 25 most recent of 270 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211452 | Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts | Ruilong Xie, Reinaldo Vega, Chanro Park, Juntao Li | 2021-12-28 |
| 11211291 | Via formation with robust hardmask removal | Ruilong Xie, Christopher J. Waskiewicz, Chih-Chao Yang | 2021-12-28 |
| 11211462 | Using selectively formed cap layers to form self-aligned contacts to source/drain regions | Chanro Park, Choonghyun Lee, Ruilong Xie | 2021-12-28 |
| 11205592 | Self-aligned top via structure | Ruilong Xie, Cheng Chi, Chih-Chao Yang | 2021-12-21 |
| 11205590 | Self-aligned contacts for MOL | Su Chen Fan, Adra Carr, Ruilong Xie | 2021-12-21 |
| 11201089 | Robust low-k bottom spacer for VFET | Hiroaki Niimi, Pietro Montanini | 2021-12-14 |
| 11201231 | Silicon germanium alloy fins with reduced defects | Hong He, Juntao Li | 2021-12-14 |
| 11196001 | 3D ReRAM formed by metal-assisted chemical etching with replacement wordline and wordline separation | Xin Miao, Wenyu Xu, Chen Zhang | 2021-12-07 |
| 11196575 | On-chipset certification to prevent spy chip | — | 2021-12-07 |
| 11195753 | Tiered-profile contact for semiconductor | Kisik Choi | 2021-12-07 |
| 11195754 | Transistor with reduced gate resistance and improved process margin of forming self-aligned contact | Zhenxing Bi, Juntao Li, Dexin Kong | 2021-12-07 |
| 11195746 | Nanosheet transistor with self-aligned dielectric pillar | Ruilong Xie, Julien Frougier | 2021-12-07 |
| 11195745 | Forming single and double diffusion breaks for fin field-effect transistor structures | Juntao Li, Ruilong Xie, Junli Wang | 2021-12-07 |
| 11195912 | Inner spacer for nanosheet transistors | Choonghyun Lee, Juntao Li, Peng Xu | 2021-12-07 |
| 11195755 | Field effect transistor devices with self-aligned source/drain contacts and gate contacts positioned over active transistors | Juntao Li, Zhenxing Bi, Dexin Kong | 2021-12-07 |
| 11189724 | Method of forming a top epitaxy source/drain structure for a vertical transistor | Dexin Kong, Shogo Mochizuki | 2021-11-30 |
| 11189729 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu | 2021-11-30 |
| 11189713 | Nanosheet transistor having wrap-around bottom isolation | Ruilong Xie, Lan Yu, Heng Wu | 2021-11-30 |
| 11189693 | Transistor having reduced contact resistance | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2021-11-30 |
| 11183581 | Vertical field effect transistor having improved uniformity | Juntao Li, Ruilong Xie, Chanro Park | 2021-11-23 |
| 11183561 | Nanosheet transistor with inner spacers | Ruilong Xie, Chanro Park, Juntao Li | 2021-11-23 |
| 11183577 | Formation of air gap spacers for reducing parasitic capacitance | Peng Xu, Choonghyun Lee, Heng Wu | 2021-11-23 |
| 11183578 | Contact over active gate employing a stacked spacer | — | 2021-11-23 |
| 11183636 | Techniques for forming RRAM cells | Juntao Li, Dexin Kong, Takashi Ando | 2021-11-23 |
| 11183430 | Self-limiting liners for increasing contact trench volume in n-type and p-type transistors | Choonghyun Lee, Juntao Li, Peng Xu | 2021-11-23 |