Issued Patents 2021
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11201092 | Gate channel length control in VFET | Choonghyun Lee, Soon-Cheon Seo, Alexander Reznicek | 2021-12-14 |
| 11196000 | Low forming voltage non-volatile memory (NVM) | Youngseok Kim, Alexander Reznicek, Soon-Cheon Seo | 2021-12-07 |
| 11177437 | Alignment through topography on intermediate component for memory device patterning | Hao Tang, Michael Rizzolo, Theodorus E. Standaert | 2021-11-16 |
| 11158788 | Atomic layer deposition and physical vapor deposition bilayer for additive patterning | Kevin W. Brew, Iqbal Rashid Saraf, Nicole Saulnier, Praneet Adusumilli | 2021-10-26 |
| 11139380 | Vertical fin-type bipolar junction transistor with self-aligned base contact | Choonghyun Lee, Seyoung Kim, Soon-Cheon Seo | 2021-10-05 |
| 11069686 | Techniques for enhancing vertical gate-all-around FET performance | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2021-07-20 |
| 11063216 | Confined phase change memory with double air gap | Balasubramanian Pranatharthiharan, Wei Wang | 2021-07-13 |
| 11043598 | Vertical field effect transistor with low-resistance bottom source-drain contact | Choonghyun Lee, Soon-Cheon Seo, Alexander Reznicek | 2021-06-22 |
| 11038064 | Vertical nano-wire complimentary metal-oxide-semiconductor transistor with cylindrical III-V compound and germanium channel | Choonghyun Lee, Soon-Cheon Seo | 2021-06-15 |
| 11038055 | Method and structure of improving contact resistance for passive and long channel devices | Soon-Cheon Seo, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2021-06-15 |
| 11011429 | Minimize middle-of-line contact line shorts | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty | 2021-05-18 |
| 10991537 | Vertical vacuum channel transistor | Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim | 2021-04-27 |
| 10985257 | Vertical transport fin field effect transistor with asymmetric channel profile | Choonghyun Lee, Brent A. Anderson, Soon-Cheon Seo | 2021-04-20 |
| 10971585 | Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between adjacent gates | Choonghyun Lee, Soon-Cheon Seo, Wenyu Xu | 2021-04-06 |
| 10950549 | ILD gap fill for memory device stack array | Soon-Cheon Seo, Alexander Reznicek, Choonghyun Lee | 2021-03-16 |
| 10937861 | Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty | 2021-03-02 |
| 10937961 | Structure and method to form bi-layer composite phase-change-memory cell | Myung-Hee Na, Nicole Saulnier, Balasubramanian Pranatharthiharan | 2021-03-02 |