Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
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Vijay Narayanan

IBM: 15 patents #229 of 11,638Top 2%
TLTokyo Electron Limited: 1 patents #275 of 787Top 35%
ULUlvac: 1 patents #11 of 68Top 20%
San Jose, CA: #61 of 6,693 inventorsTop 1%
California: #462 of 66,859 inventorsTop 1%
Overall (2021): #2,913 of 548,734Top 1%
16 Patents 2021

Issued Patents 2021

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
11195762 Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device Ruqiang Bao, Terence B. Hook, Hemanth Jagannathan 2021-12-07
11195929 Conformal replacement gate electrode for short channel devices Takashi Ando, Ruqiang Bao, Masanobu Hatanaka, Yohei Ogawa, John Rozen 2021-12-07
11158795 Resistive switching memory with replacement metal electrode Takashi Ando, Hiroyuki Miyazoe, Seyoung Kim 2021-10-26
11152214 Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device Takashi Ando, John Bruley, Eduard A. Cartier, Martin M. Frank, John Rozen 2021-10-19
11121209 Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor Takashi Ando, Eduard A. Cartier, Hemanth Jagannathan, Paul C. Jamison 2021-09-14
11043535 High-resistance memory devices Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe 2021-06-22
11031301 Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages Ruqiang Bao, Unoh Kwon 2021-06-08
10997321 Encryption engine with an undetectable/tamper proof private key in late node CMOS technology Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Singh Jutla +10 more 2021-05-04
10991881 Method for controlling the forming voltage in resistive random access memory devices Steven P. Consiglio, Cory Wajda, Kandabara Tapily, Takaaki Tsunomura, Takashi Ando +3 more 2021-04-27
10985075 Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages Ruqiang Bao, Unoh Kwon 2021-04-20
10978551 Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor Takashi Ando, Eduard A. Cartier, Hemanth Jagannathan, Paul C. Jamison 2021-04-13
10957937 Three-terminal copper-driven neuromorphic device Teodor K. Todorov, Takashi Ando, John Rozen 2021-03-23
10957696 Self-aligned metal gate with poly silicide for vertical transport field-effect transistors Brent A. Anderson, Ruqiang Bao, Dechao Guo 2021-03-23
10916432 Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, Choonghyun Lee 2021-02-09
10903425 Oxygen vacancy and filament-loss protection for resistive switching devices Takashi Ando, Hiroyuki Miyazoe, Seyoung Kim 2021-01-26
10892339 Gate first technique in vertical transport FET using doped silicon gates with silicide Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, Choonghyun Lee, Sanjay C. Mehta 2021-01-12