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Differing device characteristics on a single wafer by selective etch |
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Vertical transport field effect transistor with bottom source/drain |
Heng Wu, Lan Yu, Ruilong Xie |
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Formation of stacked vertical transport field effect transistors |
Heng Wu, Tenko Yamashita |
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Interface charge reduction for SiGe surface |
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Hybrid BEOL metallization utilizing selective reflection mask |
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Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS |
Choonghyun Lee, Ruqiang Bao, Dechao Guo |
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Semiconductor device with mitigated local layout effects |
Huimei Zhou, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu +1 more |
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